33 #if defined( CMU_PRESENT )
59 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
61 #define CMU_MAX_FREQ_0WS 26000000
63 #define CMU_MAX_FREQ_1WS 40000000
64 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
66 #define CMU_MAX_FREQ_0WS 16000000
68 #define CMU_MAX_FREQ_1WS 32000000
70 #error "Unkown MCU platform."
73 #if defined( CMU_CTRL_HFLE )
76 #if defined( _EFM32_WONDER_FAMILY ) \
77 || defined( _EZR32_LEOPARD_FAMILY ) \
78 || defined( _EZR32_WONDER_FAMILY )
79 #define CMU_MAX_FREQ_HFLE() 24000000
80 #elif defined ( _EFM32_GIANT_FAMILY )
81 #define CMU_MAX_FREQ_HFLE() (maxFreqHfle())
83 #error Invalid part/device.
91 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
111 static uint32_t auxClkGet(
void)
115 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
118 #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
120 switch(
CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
122 case CMU_AUXHFRCOCTRL_BAND_1MHZ:
126 case CMU_AUXHFRCOCTRL_BAND_7MHZ:
130 case CMU_AUXHFRCOCTRL_BAND_11MHZ:
134 case CMU_AUXHFRCOCTRL_BAND_14MHZ:
138 case CMU_AUXHFRCOCTRL_BAND_21MHZ:
142 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
143 case CMU_AUXHFRCOCTRL_BAND_28MHZ:
171 static uint32_t dbgClkGet(
void)
183 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
185 ret = ret / (1 + ((
CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
186 >> _CMU_CTRL_HFCLKDIV_SHIFT));
211 static void flashWaitStateControl(uint32_t coreFreq)
215 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
220 mscLocked =
MSC->LOCK;
225 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
230 #if defined( MSC_READCTRL_MODE_WS2 )
231 case MSC_READCTRL_MODE_WS2:
244 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
248 #if defined( MSC_READCTRL_MODE_WS2 )
249 else if (coreFreq > CMU_MAX_FREQ_1WS)
251 mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
254 else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
268 #if defined( MSC_READCTRL_MODE_WS2 )
269 else if (coreFreq > CMU_MAX_FREQ_1WS)
271 mode = MSC_READCTRL_MODE_WS2;
274 else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
301 static void flashWaitStateMax(
void)
327 #if defined( _CMU_LFCCLKEN0_MASK )
330 #if defined( _CMU_LFECLKSEL_MASK )
346 #if defined( _CMU_LFCLKSEL_MASK )
347 sel = (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;
348 #elif defined( _CMU_LFACLKSEL_MASK )
356 #if defined( _CMU_LFCLKSEL_MASK )
357 sel = (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;
358 #elif defined( _CMU_LFBCLKSEL_MASK )
365 #if defined( _CMU_LFCCLKEN0_MASK )
367 sel = (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;
371 #if defined( _CMU_LFECLKSEL_MASK )
383 #if defined( _CMU_LFCLKSEL_MASK )
386 case _CMU_LFCLKSEL_LFA_LFRCO:
390 case _CMU_LFCLKSEL_LFA_LFXO:
394 #if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
395 case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
396 #if defined( CMU_CTRL_HFLE )
399 if(((
CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK)
400 == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)
401 || (
CMU->CTRL & CMU_CTRL_HFLE))
415 case _CMU_LFCLKSEL_LFA_DISABLED:
417 #if defined( CMU_LFCLKSEL_LFAE )
422 ? _CMU_LFCLKSEL_LFAE_SHIFT
423 : _CMU_LFCLKSEL_LFBE_SHIFT))
438 #if defined( _CMU_LFACLKSEL_MASK )
453 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
454 case _CMU_LFACLKSEL_LFA_HFCLKLE:
460 #elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
479 #if defined( CMU_CTRL_HFLE ) \
480 && !defined( _EFM32_WONDER_FAMILY ) \
481 && !defined( _EZR32_LEOPARD_FAMILY ) \
482 && !defined( _EZR32_WONDER_FAMILY )
487 static uint32_t maxFreqHfle(
void)
489 uint16_t majorMinorRev;
504 if (majorMinorRev >= 0x0204)
529 __STATIC_INLINE
void syncReg(uint32_t mask)
538 while (
CMU->SYNCBUSY & mask)
544 #if defined(USB_PRESENT)
552 static uint32_t usbCClkGet(
void)
587 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
595 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(
void)
597 return (CMU_AUXHFRCOBand_TypeDef)((
CMU->AUXHFRCOCTRL
598 & _CMU_AUXHFRCOCTRL_BAND_MASK)
599 >> _CMU_AUXHFRCOCTRL_BAND_SHIFT);
604 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
613 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
620 case cmuAUXHFRCOBand_1MHz:
621 tuning = (
DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)
622 >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
625 case cmuAUXHFRCOBand_7MHz:
626 tuning = (
DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK)
627 >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
630 case cmuAUXHFRCOBand_11MHz:
631 tuning = (
DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK)
632 >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
635 case cmuAUXHFRCOBand_14MHz:
636 tuning = (
DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK)
637 >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
640 case cmuAUXHFRCOBand_21MHz:
641 tuning = (
DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK)
642 >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
645 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
646 case cmuAUXHFRCOBand_28MHz:
647 tuning = (
DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
648 >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
658 CMU->AUXHFRCOCTRL = (
CMU->AUXHFRCOCTRL &
659 ~(_CMU_AUXHFRCOCTRL_BAND_MASK
661 | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)
668 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
717 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
732 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
746 EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
774 CMU->AUXHFRCOCTRL = freqCal;
834 CMU->CALCNT = HFCycles;
839 #if defined( CMU_STATUS_CALRDY )
855 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
886 uint32_t calCtrl =
CMU->CALCTRL
921 CMU->CALCNT = downCycles;
951 CMU->CALCTRL = calCtrl;
973 #if defined( CMU_CALCTRL_CONT )
976 #if defined( CMU_STATUS_CALRDY )
1011 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1014 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
1019 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1023 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1024 case CMU_HFCLKDIV_REG:
1025 ret = 1 + ((
CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
1026 >> _CMU_CTRL_HFCLKDIV_SHIFT);
1030 case CMU_HFPERCLKDIV_REG:
1032 & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1033 >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
1037 case CMU_HFCORECLKDIV_REG:
1039 & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
1040 >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
1044 case CMU_LFAPRESC0_REG:
1049 >> _CMU_LFAPRESC0_RTC_SHIFT);
1053 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1061 #if defined(_CMU_LFAPRESC0_LCD_MASK)
1062 case cmuClock_LCDpre:
1064 >> _CMU_LFAPRESC0_LCD_SHIFT)
1070 #if defined(_CMU_LFAPRESC0_LESENSE_MASK)
1071 case cmuClock_LESENSE:
1073 >> _CMU_LFAPRESC0_LESENSE_SHIFT);
1085 case CMU_LFBPRESC0_REG:
1088 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1096 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1097 case cmuClock_LEUART1:
1099 >> _CMU_LFBPRESC0_LEUART1_SHIFT);
1143 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1146 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
1151 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1155 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1156 case CMU_HFCLKDIV_REG:
1160 flashWaitStateMax();
1163 CMU->CTRL = (
CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
1164 | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
1171 flashWaitStateControl(freq);
1175 case CMU_HFPERCLKDIV_REG:
1179 CMU->HFPERCLKDIV = (
CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1180 | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
1183 case CMU_HFCORECLKDIV_REG:
1187 flashWaitStateMax();
1189 #if defined( CMU_CTRL_HFLE )
1199 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);
1208 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
1215 CMU->HFCORECLKDIV = (
CMU->HFCORECLKDIV
1216 & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
1217 | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
1224 flashWaitStateControl(freq);
1227 case CMU_LFAPRESC0_REG:
1239 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
1240 | (div << _CMU_LFAPRESC0_RTC_SHIFT);
1243 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1258 #if defined(LCD_PRESENT)
1259 case cmuClock_LCDpre:
1268 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
1270 << _CMU_LFAPRESC0_LCD_SHIFT);
1274 #if defined(LESENSE_PRESENT)
1275 case cmuClock_LESENSE:
1284 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
1285 | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
1295 case CMU_LFBPRESC0_REG:
1298 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1313 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1314 case cmuClock_LEUART1:
1323 CMU->LFBPRESC0 = (
CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
1324 | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
1371 volatile uint32_t *reg;
1376 switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
1378 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1379 case CMU_CTRL_EN_REG:
1384 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1385 case CMU_HFCORECLKEN0_EN_REG:
1386 reg = &
CMU->HFCORECLKEN0;
1387 #if defined( CMU_CTRL_HFLE )
1397 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
1403 #if defined( _CMU_HFBUSCLKEN0_MASK )
1404 case CMU_HFBUSCLKEN0_EN_REG:
1405 reg = &
CMU->HFBUSCLKEN0;
1409 #if defined( _CMU_HFRADIOCLKEN0_MASK )
1410 case CMU_HFRADIOCLKEN0_EN_REG:
1411 reg = &
CMU->HFRADIOCLKEN0;
1415 #if defined( _CMU_HFPERCLKDIV_MASK )
1416 case CMU_HFPERCLKDIV_EN_REG:
1417 reg = &
CMU->HFPERCLKDIV;
1421 case CMU_HFPERCLKEN0_EN_REG:
1422 reg = &
CMU->HFPERCLKEN0;
1425 case CMU_LFACLKEN0_EN_REG:
1426 reg = &
CMU->LFACLKEN0;
1430 case CMU_LFBCLKEN0_EN_REG:
1431 reg = &
CMU->LFBCLKEN0;
1435 #if defined( _CMU_LFCCLKEN0_MASK )
1436 case CMU_LFCCLKEN0_EN_REG:
1437 reg = &
CMU->LFCCLKEN0;
1438 sync = CMU_SYNCBUSY_LFCCLKEN0;
1442 #if defined( _CMU_LFECLKEN0_MASK )
1443 case CMU_LFECLKEN0_EN_REG:
1444 reg = &
CMU->LFECLKEN0;
1449 case CMU_PCNT_EN_REG:
1450 reg = &
CMU->PCNTCTRL;
1459 bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
1486 switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
1488 case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1490 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1492 ret = ret / (1U + ((
CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
1493 >> _CMU_CTRL_HFCLKDIV_SHIFT));
1495 #if defined( _CMU_HFPRESC_MASK )
1501 case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1503 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1504 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1506 ret = ret / (1U + ((
CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
1507 >> _CMU_CTRL_HFCLKDIV_SHIFT));
1509 ret >>= (
CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1510 >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
1511 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1517 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1518 #if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
1519 case (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1521 ret /= 1U + ((
CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
1522 >> _CMU_HFRADIOPRESC_PRESC_SHIFT);
1526 #if defined( CRYPTO_PRESENT ) \
1527 || defined( LDMA_PRESENT ) \
1528 || defined( GPCRC_PRESENT ) \
1529 || defined( PRS_PRESENT ) \
1530 || defined( GPIO_PRESENT )
1531 case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1536 case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1542 case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1549 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1550 #if defined(AES_PRESENT) \
1551 || defined(DMA_PRESENT) \
1552 || defined(EBI_PRESENT) \
1553 || defined(USB_PRESENT)
1554 case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1561 case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1565 #if defined( _CMU_LFACLKEN0_RTC_MASK )
1566 case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1568 ret >>= (
CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
1569 >> _CMU_LFAPRESC0_RTC_SHIFT;
1573 #if defined( _CMU_LFECLKEN0_RTCC_MASK )
1574 case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1579 #if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
1580 case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1582 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1585 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1592 #if defined(_CMU_LFACLKEN0_LCD_MASK)
1593 case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1595 ret >>= ((
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1596 >> _CMU_LFAPRESC0_LCD_SHIFT)
1600 case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1602 ret >>= (
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1603 >> _CMU_LFAPRESC0_LCD_SHIFT;
1604 ret /= 1U + ((
CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)
1605 >> _CMU_LCDCTRL_FDIV_SHIFT);
1609 #if defined(_CMU_LFACLKEN0_LESENSE_MASK)
1610 case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1612 ret >>= (
CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1613 >> _CMU_LFAPRESC0_LESENSE_SHIFT;
1617 case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1621 #if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
1622 case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1624 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1627 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1634 #if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
1635 case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1637 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1638 ret >>= (
CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1639 >> _CMU_LFBPRESC0_LEUART1_SHIFT;
1640 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1642 >> _CMU_LFBPRESC0_LEUART1_SHIFT);
1647 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1648 case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1653 case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1657 case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1661 #if defined(USB_PRESENT)
1662 case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1677 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1696 prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1700 case CMU_HFPRESC_REG:
1705 case CMU_HFEXPPRESC_REG:
1710 case CMU_HFCLKLEPRESC_REG:
1715 case CMU_HFPERPRESC_REG:
1720 #if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
1721 case CMU_HFRADIOPRESC_REG:
1722 ret = ((
CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
1723 >> _CMU_HFRADIOPRESC_PRESC_SHIFT);
1727 case CMU_HFCOREPRESC_REG:
1732 case CMU_LFAPRESC0_REG:
1735 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
1751 case CMU_LFBPRESC0_REG:
1754 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
1763 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
1764 case cmuClock_LEUART1:
1765 ret = (((
CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1766 >> _CMU_LFBPRESC0_LEUART1_SHIFT));
1779 case CMU_LFEPRESC0_REG:
1782 #if defined( RTCC_PRESENT )
1808 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1833 prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1837 case CMU_HFPRESC_REG:
1838 EFM_ASSERT(presc < 32U);
1844 case CMU_HFEXPPRESC_REG:
1845 EFM_ASSERT(presc < 32U);
1851 case CMU_HFCLKLEPRESC_REG:
1852 EFM_ASSERT(presc < 2U);
1860 case CMU_HFPERPRESC_REG:
1861 EFM_ASSERT(presc < 512U);
1867 #if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
1868 case CMU_HFRADIOPRESC_REG:
1869 EFM_ASSERT(presc < 512U);
1871 CMU->HFRADIOPRESC = (
CMU->HFRADIOPRESC & ~_CMU_HFRADIOPRESC_PRESC_MASK)
1872 | (presc << _CMU_HFRADIOPRESC_PRESC_SHIFT);
1876 case CMU_HFCOREPRESC_REG:
1877 EFM_ASSERT(presc < 512U);
1881 flashWaitStateControl(CMU_MAX_FREQ_0WS + 1);
1891 flashWaitStateControl(freq);
1894 case CMU_LFAPRESC0_REG:
1897 #if defined( RTC_PRESENT )
1899 EFM_ASSERT(presc <= 32768U);
1907 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
1908 | (presc << _CMU_LFAPRESC0_RTC_SHIFT);
1912 #if defined( RTCC_PRESENT )
1914 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
1916 EFM_ASSERT(presc <= 0U);
1924 EFM_ASSERT(presc <= 32768U);
1932 CMU->LFAPRESC0 = (
CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
1933 | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
1938 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
1940 EFM_ASSERT(presc <= 32768U);
1959 case CMU_LFBPRESC0_REG:
1962 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
1964 EFM_ASSERT(presc <= 8U);
1977 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
1978 case cmuClock_LEUART1:
1979 EFM_ASSERT(presc <= 8U);
1987 CMU->LFBPRESC0 = (
CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
1988 | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
1998 case CMU_LFEPRESC0_REG:
2001 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
2003 EFM_ASSERT(presc <= 0U);
2053 selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2057 case CMU_HFCLKSEL_REG:
2058 #if defined( _CMU_HFCLKSEL_HF_MASK )
2079 & (CMU_STATUS_HFRCOSEL
2080 | CMU_STATUS_HFXOSEL
2081 | CMU_STATUS_LFRCOSEL
2082 #
if defined( CMU_STATUS_USHFRCODIV2SEL )
2083 | CMU_STATUS_USHFRCODIV2SEL
2085 | CMU_STATUS_LFXOSEL))
2087 case CMU_STATUS_LFXOSEL:
2091 case CMU_STATUS_LFRCOSEL:
2095 case CMU_STATUS_HFXOSEL:
2099 #if defined( CMU_STATUS_USHFRCODIV2SEL )
2100 case CMU_STATUS_USHFRCODIV2SEL:
2101 ret = cmuSelect_USHFRCODIV2;
2112 case CMU_LFACLKSEL_REG:
2113 #if defined( _CMU_LFCLKSEL_MASK )
2114 switch (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
2116 case CMU_LFCLKSEL_LFA_LFRCO:
2120 case CMU_LFCLKSEL_LFA_LFXO:
2124 #if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
2125 case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
2131 #if defined( CMU_LFCLKSEL_LFAE )
2132 if (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
2144 #if defined( _CMU_LFACLKSEL_MASK )
2159 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2160 case CMU_LFACLKSEL_LFA_HFCLKLE:
2172 case CMU_LFBCLKSEL_REG:
2173 #if defined( _CMU_LFCLKSEL_MASK )
2174 switch (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
2176 case CMU_LFCLKSEL_LFB_LFRCO:
2180 case CMU_LFCLKSEL_LFB_LFXO:
2184 #if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
2185 case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
2190 #if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
2191 case CMU_LFCLKSEL_LFB_HFCLKLE:
2197 #if defined( CMU_LFCLKSEL_LFBE )
2198 if (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
2210 #if defined( _CMU_LFBCLKSEL_MASK )
2236 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2237 case CMU_LFCCLKSEL_REG:
2238 switch (
CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
2240 case CMU_LFCLKSEL_LFC_LFRCO:
2244 case CMU_LFCLKSEL_LFC_LFXO:
2255 #if defined( _CMU_LFECLKSEL_LFE_MASK )
2256 case CMU_LFECLKSEL_REG:
2271 #if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
2272 case CMU_LFECLKSEL_LFE_HFCLKLE:
2284 case CMU_DBGCLKSEL_REG:
2285 #if defined( _CMU_DBGCLKSEL_DBG_MASK )
2300 #if defined( _CMU_CTRL_DBGCLK_MASK )
2301 switch(
CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
2303 case CMU_CTRL_DBGCLK_AUXHFRCO:
2307 case CMU_CTRL_DBGCLK_HFCLK:
2317 #if defined( USB_PRESENT )
2318 case CMU_USBCCLKSEL_REG:
2320 & (CMU_STATUS_USBCLFXOSEL
2321 #
if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2322 | CMU_STATUS_USBCHFCLKSEL
2324 #
if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
2325 | CMU_STATUS_USBCUSHFRCOSEL
2327 | CMU_STATUS_USBCLFRCOSEL))
2329 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2330 case CMU_STATUS_USBCHFCLKSEL:
2335 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
2336 case CMU_STATUS_USBCUSHFRCOSEL:
2337 ret = cmuSelect_USHFRCO;
2341 case CMU_STATUS_USBCLFXOSEL:
2345 case CMU_STATUS_USBCLFRCOSEL:
2413 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2414 volatile uint32_t *selReg = NULL;
2416 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2417 uint32_t lfExtended = 0;
2420 selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2424 case CMU_HFCLKSEL_REG:
2428 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2430 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2431 select = CMU_CMD_HFCLKSEL_LFXO;
2437 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2439 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2440 select = CMU_CMD_HFCLKSEL_LFRCO;
2447 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2455 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2456 select = CMU_CMD_HFCLKSEL_HFXO;
2457 #if defined( CMU_CTRL_HFLE )
2462 CMU->CTRL = (
CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
2463 | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ
2469 if (
CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)
2472 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
2479 CMU->CTRL = (
CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
2480 | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
2487 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2489 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2490 select = CMU_CMD_HFCLKSEL_HFRCO;
2495 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
2496 case cmuSelect_USHFRCODIV2:
2497 select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
2498 osc = cmuOsc_USHFRCO;
2502 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
2518 flashWaitStateMax();
2521 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2522 CMU->HFCLKSEL = select;
2523 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2535 flashWaitStateControl(freq);
2538 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2539 case CMU_LFACLKSEL_REG:
2540 selReg = (selReg == NULL) ? &
CMU->LFACLKSEL : selReg;
2541 #
if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2545 case CMU_LFECLKSEL_REG:
2546 selReg = (selReg == NULL) ? &
CMU->LFECLKSEL : selReg;
2547 #
if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
2551 case CMU_LFBCLKSEL_REG:
2552 selReg = (selReg == NULL) ? &
CMU->LFBCLKSEL : selReg;
2578 if (freq > 32000000U)
2600 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2601 case CMU_LFACLKSEL_REG:
2602 case CMU_LFBCLKSEL_REG:
2606 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
2612 tmp = _CMU_LFCLKSEL_LFA_LFXO;
2618 tmp = _CMU_LFCLKSEL_LFA_LFRCO;
2624 tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
2625 #if defined( CMU_CTRL_HFLE )
2629 if(freq > CMU_MAX_FREQ_HFLE())
2636 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
2641 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2644 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
2656 if (selRegId == CMU_LFACLKSEL_REG)
2658 #if defined( _CMU_LFCLKSEL_LFAE_MASK )
2659 CMU->LFCLKSEL = (
CMU->LFCLKSEL
2660 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK))
2661 | (tmp << _CMU_LFCLKSEL_LFA_SHIFT)
2662 | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
2664 CMU->LFCLKSEL = (
CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)
2665 | (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
2670 #if defined( _CMU_LFCLKSEL_LFBE_MASK )
2671 CMU->LFCLKSEL = (
CMU->LFCLKSEL
2672 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK))
2673 | (tmp << _CMU_LFCLKSEL_LFB_SHIFT)
2674 | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
2676 CMU->LFCLKSEL = (
CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK)
2677 | (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
2682 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2683 case CMU_LFCCLKSEL_REG:
2687 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
2693 tmp = _CMU_LFCLKSEL_LFC_LFXO;
2699 tmp = _CMU_LFCLKSEL_LFC_LFRCO;
2709 CMU->LFCLKSEL = (
CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK)
2710 | (tmp << _CMU_LFCLKSEL_LFC_SHIFT);
2715 #if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )
2716 case CMU_DBGCLKSEL_REG:
2719 #if defined( CMU_DBGCLKSEL_DBG )
2731 #if defined( CMU_CTRL_DBGCLK )
2734 CMU->CTRL = (
CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2735 | CMU_CTRL_DBGCLK_AUXHFRCO;
2740 CMU->CTRL = (
CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2741 | CMU_CTRL_DBGCLK_HFCLK;
2753 #if defined(USB_PRESENT)
2754 case CMU_USBCCLKSEL_REG:
2763 CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
2766 while((
CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)
2777 CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
2780 while((
CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)
2785 #if defined( CMU_STATUS_USBCHFCLKSEL )
2789 CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
2791 while((
CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
2797 #if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
2798 case cmuSelect_USHFRCO:
2804 CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
2807 while((
CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)
2868 while (
CMU->SYNCBUSY)
2881 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
2889 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(
void)
2891 return (CMU_HFRCOBand_TypeDef)((
CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
2892 >> _CMU_HFRCOCTRL_BAND_SHIFT);
2897 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
2906 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
2915 case cmuHFRCOBand_1MHz:
2916 tuning = (
DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)
2917 >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
2920 case cmuHFRCOBand_7MHz:
2921 tuning = (
DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK)
2922 >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT;
2925 case cmuHFRCOBand_11MHz:
2926 tuning = (
DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK)
2927 >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT;
2930 case cmuHFRCOBand_14MHz:
2931 tuning = (
DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK)
2932 >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT;
2935 case cmuHFRCOBand_21MHz:
2936 tuning = (
DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)
2937 >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
2940 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
2941 case cmuHFRCOBand_28MHz:
2942 tuning = (
DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
2943 >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
2957 flashWaitStateMax();
2961 CMU->HFRCOCTRL = (
CMU->HFRCOCTRL &
2963 | (band << _CMU_HFRCOCTRL_BAND_SHIFT)
2976 flashWaitStateControl(freq);
2982 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
3056 EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
3062 flashWaitStateMax();
3070 EFM_ASSERT(freqCal != UINT_MAX);
3093 CMU->HFRCOCTRL = freqCal;
3099 flashWaitStateControl((uint32_t)freq);
3104 #if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
3115 uint32_t CMU_HFRCOStartupDelayGet(
void)
3117 return (
CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK)
3118 >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
3132 void CMU_HFRCOStartupDelaySet(uint32_t delay)
3134 EFM_ASSERT(delay <= 31);
3136 delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
3137 CMU->HFRCOCTRL = (
CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK))
3138 | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
3143 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
3166 bool enEM0EM1StartSel)
3177 CMU->HFXOCTRL = hfxoCtrl;
3182 #if defined( _CMU_HFXOCTRL_MASK )
3251 ishReg = ishReg > ishMax ? ishMax : ishReg;
3297 #if defined( LCD_PRESENT )
3298 return (
CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
3320 #if defined( LCD_PRESENT )
3324 if (
CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
3329 div <<= _CMU_LCDCTRL_FDIV_SHIFT;
3330 div &= _CMU_LCDCTRL_FDIV_MASK;
3331 CMU->LCDCTRL = (
CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div;
3338 #if defined( _CMU_LFXOCTRL_MASK )
3397 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3409 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3418 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3427 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3436 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3445 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3450 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
3451 case cmuOsc_USHFRCO:
3452 enBit = CMU_OSCENCMD_USHFRCOEN;
3453 disBit = CMU_OSCENCMD_USHFRCODIS;
3454 rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;
3455 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3456 ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;
3461 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
3475 CMU->OSCENCMD = enBit;
3477 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3488 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
3507 CMU->OSCENCMD = disBit;
3509 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3592 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3603 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3616 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3649 #if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
3654 #if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
3656 setting =
CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
3659 #if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
3661 setting =
CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
3671 return (setting ?
true :
false);
3687 #if defined( PCNT_PRESENT )
3688 uint32_t setting = 0;
3706 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
3714 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(
void)
3716 return (CMU_USHFRCOBand_TypeDef)((
CMU->USHFRCOCONF
3717 & _CMU_USHFRCOCONF_BAND_MASK)
3718 >> _CMU_USHFRCOCONF_BAND_SHIFT);
3722 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
3730 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
3733 uint32_t fineTuning;
3738 EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
3743 case cmuUSHFRCOBand_24MHz:
3744 tuning = (
DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)
3745 >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
3746 fineTuning = (
DEVINFO->USHFRCOCAL0
3747 & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)
3748 >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
3751 case cmuUSHFRCOBand_48MHz:
3752 tuning = (
DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK)
3753 >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;
3754 fineTuning = (
DEVINFO->USHFRCOCAL0
3755 & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK)
3756 >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
3767 CMU->USHFRCOCONF = (
CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK)
3768 | (band << _CMU_USHFRCOCONF_BAND_SHIFT);
3769 CMU->USHFRCOCTRL = (
CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK)
3770 | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);
3771 CMU->USHFRCOTUNE = (
CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK)
3772 | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
3775 if (band == cmuUSHFRCOBand_24MHz)
uint8_t timeoutWarmSteady
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT
Clock management unit (CMU) API.
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
uint8_t xoCoreBiasTrimSteadyState
#define _CMU_HFCOREPRESC_PRESC_MASK
#define MSC_READCTRL_MODE_WS0
static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO.
#define CMU_OSCENCMD_LFRCOEN
#define CMU_CALCTRL_DOWNSEL_LFRCO
#define _CMU_HFRCOCTRL_TUNING_MASK
#define _CMU_HFXOCTRL_LOWPOWER_MASK
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK
#define _CMU_STATUS_LFXORDY_SHIFT
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK
#define CMU_LFBCLKSEL_LFB_LFXO
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT
#define _CMU_STATUS_HFRCOENS_SHIFT
uint8_t regIshSteadyState
Emlib peripheral API "assert" implementation.
#define _CMU_STATUS_HFXOENS_SHIFT
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0
#define CMU_HFPRESC_HFCLKLEPRESC_DIV4
#define _CMU_LFBCLKSEL_LFB_MASK
#define _CMU_LFBCLKSEL_LFB_SHIFT
#define _CMU_HFCOREPRESC_PRESC_SHIFT
#define _CMU_LFECLKSEL_LFE_SHIFT
#define _CMU_LFXOCTRL_TUNING_MASK
#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
#define _CMU_LFACLKSEL_LFA_MASK
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)
Calibrate clock.
#define CMU_OSCENCMD_AUXHFRCOEN
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT
#define CMU_HFCLKSEL_HF_HFRCO
#define CMU_HFXOCTRL_LOWPOWER
RAM and peripheral bit-field set and clear API.
#define CMU_LFBCLKSEL_LFB_LFRCO
#define _CMU_LFRCOCTRL_TUNING_SHIFT
#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT
#define _ROMTABLE_PID0_REVMAJOR_SHIFT
#define _CMU_LFXOCTRL_TIMEOUT_MASK
#define _CMU_LFACLKSEL_LFA_ULFRCO
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2
#define _ROMTABLE_PID3_REVMINORLSB_MASK
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1
#define _CMU_STATUS_LFXOENS_SHIFT
#define CMU_OSCENCMD_HFXODIS
static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
Get a pointer to the HFRCO frequency calibration word in DEVINFO.
#define CMU_SYNCBUSY_LFECLKEN0
#define _ROMTABLE_PID2_REVMINORMSB_MASK
#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT
#define CMU_OSCENCMD_AUXHFRCODIS
#define _CMU_CALCNT_CALCNT_SHIFT
uint32_t SystemMaxCoreClockGet(void)
Get the maximum core clock frequency.
uint32_t SystemHfrcoFreq
System HFRCO frequency.
#define _CMU_HFPRESC_PRESC_SHIFT
#define CMU_CALCTRL_UPSEL_AUXHFRCO
#define _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK
void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc)
Set clock prescaler.
#define CMU_SYNCBUSY_LFEPRESC0
#define _CMU_HFPERPRESC_PRESC_MASK
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4
#define CMU_HFRCOCTRL_CLKDIV_DIV2
uint8_t thresholdPeakDetect
#define _CMU_LFBCLKSEL_LFB_HFCLKLE
#define _CMU_LFXOCTRL_GAIN_SHIFT
#define _CMU_LFBPRESC0_LEUART0_MASK
void CMU_FreezeEnable(bool enable)
CMU low frequency register synchronization freeze control.
uint32_t SystemHFXOClockGet(void)
Get high frequency crystal oscillator clock frequency for target system.
#define _CMU_DBGCLKSEL_DBG_MASK
#define _CMU_CTRL_WSHFLE_SHIFT
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
#define _CMU_HFRCOCTRL_TUNING_SHIFT
bool autoStartSelOnRacWakeup
#define CMU_DBGCLKSEL_DBG_AUXHFRCO
#define CMU_SYNCBUSY_LFBPRESC0
void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit)
Set HFXO control registers.
void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freqEnum)
Set AUXHFRCO calibration for the selected target frequency.
uint32_t CMU_ClkDiv_TypeDef
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
#define _CMU_LFECLKSEL_LFE_MASK
#define CMU_DBGCLKSEL_DBG_HFCLK
#define _CMU_STATUS_HFRCORDY_SHIFT
#define _CMU_STATUS_HFXORDY_SHIFT
#define _CMU_STATUS_AUXHFRCOENS_SHIFT
__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Convert logarithm of 2 prescaler to division factor.
#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK
#define CMU_CALCTRL_UPSEL_LFXO
#define _CMU_CALCTRL_CONT_SHIFT
#define CMU_OSCENCMD_HFXOEN
#define _CMU_HFBUSCLKEN0_LE_SHIFT
void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freqEnum)
Set HFRCO calibration for the selected target frequency.
#define _CMU_HFCLKSEL_HF_MASK
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
Set the oscillator frequency tuning control.
#define CMU_LFECLKSEL_LFE_LFXO
CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
Get AUXHFRCO frequency enumeration in use.
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK
void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit)
Set LFXO control registers.
#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT
#define CMU_LFECLKSEL_LFE_LFRCO
__STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
Get family identifier of the MCU.
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)
Configure clock calibration.
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
#define _CMU_HFPERPRESC_PRESC_SHIFT
#define _CMU_LFXOCTRL_TIMEOUT_SHIFT
#define CMU_CALCTRL_UPSEL_HFRCO
#define _CMU_STATUS_CALRDY_SHIFT
uint8_t timeoutPeakDetect
#define _CMU_CALCTRL_DOWNSEL_MASK
#define CMU_FREEZE_REGFREEZE
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1
#define CMU_OSCENCMD_LFXODIS
#define CMU_CALCTRL_UPSEL_LFRCO
#define _CMU_STATUS_LFRCOENS_SHIFT
CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
Get HFRCO frequency enumeration in use.
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT
#define _CMU_HFPRESC_HFCLKLEPRESC_MASK
#define _CMU_HFEXPPRESC_PRESC_MASK
#define CMU_CALCTRL_DOWNSEL_HFRCO
uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
Get clock prescaler.
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK
#define _CMU_LFEPRESC0_RTCC_MASK
uint32_t CMU_LCDClkFDIVGet(void)
Get the LCD framerate divisor (FDIV) setting.
__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Convert dividend to logarithmic value. Only works for even numbers equal to 2^n.
#define _CMU_LFACLKSEL_LFA_DISABLED
#define CMU_LFBCLKSEL_LFB_HFCLKLE
uint32_t CMU_CalibrateCountGet(void)
Get calibration count register.
#define _CMU_STATUS_AUXHFRCORDY_SHIFT
uint32_t SystemULFRCOClockGet(void)
Get ultra low frequency RC oscillator clock frequency for target system.
uint32_t CMU_ClkPresc_TypeDef
#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT
uint8_t xoCoreBiasTrimStartup
#define CMU_SYNCBUSY_LFAPRESC0
#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
#define CMU_LFECLKSEL_LFE_ULFRCO
#define CMU_SYNCBUSY_LFBCLKEN0
#define _CMU_LFEPRESC0_RTCC_SHIFT
#define _CMU_HFEXPPRESC_PRESC_SHIFT
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1
#define CMU_SYNCBUSY_LFACLKEN0
void CMU_LCDClkFDIVSet(uint32_t div)
Set the LCD framerate divisor (FDIV) setting.
#define _CMU_LFACLKSEL_LFA_SHIFT
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT
__STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
Convert prescaler dividend to logarithmic value. Only works for even numbers equal to 2^n...
#define CMU_HFRCOCTRL_CLKDIV_DIV1
#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
#define CMU_OSCENCMD_HFRCOEN
#define CMU_OSCENCMD_LFRCODIS
#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
#define _CMU_LFAPRESC0_LETIMER0_SHIFT
#define CMU_LFACLKSEL_LFA_LFRCO
uint8_t timeoutShuntOptimization
#define CMU_CALCTRL_UPSEL_HFXO
__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, uint32_t mask)
Perform a peripheral register masked read.
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
#define CMU_CALCTRL_DOWNSEL_LFXO
#define CMU_HFXOCTRL_AUTOSTARTRDYSELRAC
Energy management unit (EMU) peripheral API.
#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT
#define MSC_READCTRL_MODE_WS1
#define CMU_HFCLKSEL_HF_LFXO
#define _ROMTABLE_PID0_REVMAJOR_MASK
#define CMU_LFACLKSEL_LFA_LFXO
#define CMU_HFCLKSEL_HF_HFXO
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT
#define CMU_CALCTRL_DOWNSEL_AUXHFRCO
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT
#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT
uint32_t SystemLFXOClockGet(void)
Get low frequency crystal oscillator clock frequency for target system.
#define CMU_HFRCOCTRL_CLKDIV_DIV4
#define _CMU_LFBPRESC0_LEUART0_SHIFT
#define _CMU_LFEPRESC0_RTCC_DIV1
#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT
#define CMU_LFBCLKSEL_LFB_ULFRCO
#define _CMU_HFRCOCTRL_CLKDIV_MASK
#define CMU_CALCTRL_DOWNSEL_HFXO
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT
#define _CMU_CALCNT_CALCNT_MASK
#define _CMU_LFRCOCTRL_TUNING_MASK
uint32_t SystemHFClockGet(void)
Get the current HFCLK frequency.
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
Get oscillator frequency tuning setting.
#define _CMU_LFXOCTRL_TUNING_SHIFT
#define _CMU_CALCTRL_UPSEL_MASK
#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT
#define CMU_OSCENCMD_HFRCODIS
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT
#define _CMU_LFACLKSEL_LFA_LFXO
#define _CMU_LFAPRESC0_LETIMER0_MASK
#define _CMU_LFXOCTRL_GAIN_MASK
uint16_t ctuneSteadyState
#define _CMU_AUXHFRCOCTRL_TUNING_MASK
bool CMU_PCNTClockExternalGet(unsigned int instance)
Determine if currently selected PCNTn clock used is external or LFBCLK.
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT
void CMU_HFXOAutostartEnable(bool enRACStartSel, bool enEM0EM1Start, bool enEM0EM1StartSel)
Enable or disable HFXO autostart.
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT
#define CMU_OSCENCMD_LFXOEN
#define _CMU_HFPRESC_PRESC_MASK
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
#define _CMU_STATUS_LFRCORDY_SHIFT
#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT
uint32_t SystemCoreClockGet(void)
Get the current core clock frequency.
#define CMU_HFCLKSEL_HF_LFRCO
#define _CMU_LFACLKSEL_LFA_LFRCO
#define _MSC_READCTRL_MODE_MASK
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
uint32_t SystemLFRCOClockGet(void)
Get low frequency RC oscillator clock frequency for target system.
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
#define CMU_LFACLKSEL_LFA_ULFRCO
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.