EFM32 Pearl Gecko Software Documentation  efm32pg1-doc-4.2.1
em_wdog.c
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1 /***************************************************************************/
34 #include "em_wdog.h"
35 #if defined(WDOG_COUNT) && (WDOG_COUNT > 0)
36 
37 #if defined(WDOG0)
38 #define WDOG WDOG0
39 #if (WDOG_COUNT > 1)
40 #warning "Multiple watchdogs not supported"
41 #endif
42 #endif
43 
44 #include "em_bus.h"
45 
46 /***************************************************************************/
51 /***************************************************************************/
57 /*******************************************************************************
58  ************************** GLOBAL FUNCTIONS *******************************
59  ******************************************************************************/
60 
61 /***************************************************************************/
75 void WDOG_Enable(bool enable)
76 {
77  if (!enable)
78  {
79  /* Wait for any pending previous write operation to have been completed in */
80  /* low frequency domain */
81  while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
82  ;
83  }
84  BUS_RegBitWrite(&(WDOG->CTRL), _WDOG_CTRL_EN_SHIFT, enable);
85 }
86 
87 
88 /***************************************************************************/
97 void WDOG_Feed(void)
98 {
99  /* The watchdog should not be fed while it is disabled */
100  if ( !(WDOG->CTRL & WDOG_CTRL_EN) )
101  {
102  return;
103  }
104 
105  /* If a previous clearing is being synchronized to LF domain, then there */
106  /* is no point in waiting for it to complete before clearing over again. */
107  /* This avoids stalling the core in the typical use case where some idle loop */
108  /* keeps clearing the watchdog. */
109  if (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CMD)
110  {
111  return;
112  }
113  /* Before writing to the WDOG_CMD register we also need to make sure that
114  * any previous write to WDOG_CTRL is complete. */
115  while ( WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL )
116  ;
117 
118  WDOG->CMD = WDOG_CMD_CLEAR;
119 }
120 
121 
122 /***************************************************************************/
137 void WDOG_Init(const WDOG_Init_TypeDef *init)
138 {
139  uint32_t setting;
140 
141  if (init->enable)
142  {
143  setting = WDOG_CTRL_EN;
144  }
145  else
146  {
147  setting = 0;
148  }
149 
150  if (init->debugRun)
151  {
152  setting |= WDOG_CTRL_DEBUGRUN;
153  }
154 
155  if (init->em2Run)
156  {
157  setting |= WDOG_CTRL_EM2RUN;
158  }
159 
160  if (init->em3Run)
161  {
162  setting |= WDOG_CTRL_EM3RUN;
163  }
164 
165  if (init->em4Block)
166  {
167  setting |= WDOG_CTRL_EM4BLOCK;
168  }
169 
170  if (init->swoscBlock)
171  {
172  setting |= WDOG_CTRL_SWOSCBLOCK;
173  }
174 
175  setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT)
176  | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
177 
178  /* Wait for any pending previous write operation to have been completed in */
179  /* low frequency domain */
180  while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
181  ;
182 
183  WDOG->CTRL = setting;
184 
185  /* Optional register locking */
186  if (init->lock)
187  {
188  if (init->enable)
189  {
190  WDOG_Lock();
191  }
192  else
193  {
194  BUS_RegBitWrite(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
195  }
196  }
197 }
198 
199 
200 /***************************************************************************/
218 void WDOG_Lock(void)
219 {
220  /* Wait for any pending previous write operation to have been completed in */
221  /* low frequency domain */
222  while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
223  ;
224 
225  /* Disable writing to the control register */
226  BUS_RegBitWrite(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
227 }
228 
229 
232 #endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */
WDOG_ClkSel_TypeDef clkSel
Definition: em_wdog.h:118
#define WDOG_SYNCBUSY_CTRL
#define WDOG_CTRL_SWOSCBLOCK
void WDOG_Feed(void)
Feed the watchdog.
Definition: em_wdog.c:97
RAM and peripheral bit-field set and clear API.
void WDOG_Enable(bool enable)
Enable/disable the watchdog timer.
Definition: em_wdog.c:75
#define WDOG_CTRL_EN
WDOG_PeriodSel_TypeDef perSel
Definition: em_wdog.h:121
void WDOG_Lock(void)
Lock the watchdog configuration.
Definition: em_wdog.c:218
#define WDOG_CTRL_EM2RUN
#define _WDOG_CTRL_EN_SHIFT
void WDOG_Init(const WDOG_Init_TypeDef *init)
Initialize watchdog (assuming the watchdog configuration has not been locked).
Definition: em_wdog.c:137
#define WDOG_CTRL_DEBUGRUN
#define _WDOG_CTRL_LOCK_SHIFT
#define WDOG_SYNCBUSY_CMD
#define _WDOG_CTRL_CLKSEL_SHIFT
#define WDOG_CTRL_EM4BLOCK
#define WDOG_CTRL_EM3RUN
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146
Watchdog (WDOG) peripheral API.
#define WDOG_CMD_CLEAR
#define _WDOG_CTRL_PERSEL_SHIFT