EFM32 Pearl Gecko Software Documentation  efm32pg1-doc-4.2.1
em_i2c.c
Go to the documentation of this file.
1 /***************************************************************************/
33 #include "em_i2c.h"
34 #if defined(I2C_COUNT) && (I2C_COUNT > 0)
35 
36 #include "em_cmu.h"
37 #include "em_bus.h"
38 #include "em_assert.h"
39 
40  #include <limits.h>
41 
42 /***************************************************************************/
47 /***************************************************************************/
53 /*******************************************************************************
54  ******************************* DEFINES ***********************************
55  ******************************************************************************/
56 
60 #if (I2C_COUNT == 1)
61 #define I2C_REF_VALID(ref) ((ref) == I2C0)
62 #elif (I2C_COUNT == 2)
63 #define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1))
64 #elif (I2C_COUNT == 3)
65 #define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1)|| (ref == I2C2))
66 #endif
67 
69 /* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
70 /* this SW supporting master mode. Likewise for I2C_IF_RXUF (receive underflow) */
71 /* RXUF is only likely to occur with this SW if using a debugger peeking into */
72 /* RXDATA register. Thus, we ignore those types of fault. */
73 #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
74 
75 /* Max I2C transmission rate constant */
76 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
77 #define I2C_CR_MAX 4
78 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
79 #define I2C_CR_MAX 8
80 #else
81 #warning "Max I2C transmission rate constant is not defined"
82 #endif
83 
86 /*******************************************************************************
87  ******************************** ENUMS ************************************
88  ******************************************************************************/
89 
93 typedef enum
94 {
95  i2cStateStartAddrSend,
96  i2cStateAddrWFAckNack,
97  i2cStateAddrWF2ndAckNack,
98  i2cStateRStartAddrSend,
99  i2cStateRAddrWFAckNack,
100  i2cStateDataSend,
101  i2cStateDataWFAckNack,
102  i2cStateWFData,
103  i2cStateWFStopSent,
104  i2cStateDone
105 } I2C_TransferState_TypeDef;
106 
109 /*******************************************************************************
110  ******************************* STRUCTS ***********************************
111  ******************************************************************************/
112 
116 typedef struct
117 {
119  I2C_TransferState_TypeDef state;
120 
123 
125  uint16_t offset;
126 
127  /* Index to current sequence buffer in use. */
128  uint8_t bufIndx;
129 
132 } I2C_Transfer_TypeDef;
133 
136 /*******************************************************************************
137  ***************************** LOCAL DATA *******^**************************
138  ******************************************************************************/
139 
146 static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 };
147 
149 static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT];
150 
153 /*******************************************************************************
154  ************************** GLOBAL FUNCTIONS *******************************
155  ******************************************************************************/
156 
157 /***************************************************************************/
171 {
172  uint32_t freqHfper;
173  uint32_t n;
174 
175  /* Max frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX)
176  * More details can be found in the reference manual,
177  * I2C Clock Generation chapter. */
178  freqHfper = CMU_ClockFreqGet(cmuClock_HFPER);
179  /* n = Nlow + Nhigh */
180  n = (uint32_t)(i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) >> _I2C_CTRL_CLHR_SHIFT]);
181 
182  return (freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX));
183 }
184 
185 
186 /***************************************************************************/
224  uint32_t freqRef,
225  uint32_t freqScl,
226  I2C_ClockHLR_TypeDef i2cMode)
227 {
228  uint32_t n, minFreq;
229  int32_t div;
230 
231  /* Avoid divide by 0 */
232  EFM_ASSERT(freqScl);
233  if (!freqScl)
234  {
235  return;
236  }
237 
238  /* Set the CLHR (clock low to high ratio). */
239  i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK;
240  BUS_RegMaskedWrite(&i2c->CTRL,
242  i2cMode <<_I2C_CTRL_CLHR_SHIFT);
243 
244  if (!freqRef)
245  {
246  freqRef = CMU_ClockFreqGet(cmuClock_HFPER);
247  }
248 
249  /* Check minumum HF peripheral clock */
250  minFreq = UINT_MAX;
251  if (i2c->CTRL & I2C_CTRL_SLAVE)
252  {
253  switch(i2cMode)
254  {
255  case i2cClockHLRStandard:
256 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
257  minFreq = 4200000; break;
258 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
259  minFreq = 2000000; break;
260 #endif
262 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
263  minFreq = 11000000; break;
264 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
265  minFreq = 5000000; break;
266 #endif
267  case i2cClockHLRFast:
268 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
269  minFreq = 24400000; break;
270 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
271  minFreq = 14000000; break;
272 #endif
273  }
274  }
275  else
276  {
277  /* For master mode, platform 1 and 2 share the same
278  min frequencies */
279  switch(i2cMode)
280  {
281  case i2cClockHLRStandard:
282  minFreq = 2000000; break;
284  minFreq = 9000000; break;
285  case i2cClockHLRFast:
286  minFreq = 20000000; break;
287  }
288  }
289 
290  /* Frequency most be larger-than */
291  EFM_ASSERT(freqRef > minFreq);
292 
293  /* SCL frequency is given by
294  * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_C_MAX)
295  *
296  * Thus
297  * DIV = ((freqRef - (I2C_C_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1
298  *
299  * More details can be found in the reference manual,
300  * I2C Clock Generation chapter. */
301 
302  /* n = Nlow + Nhigh */
303  n = (uint32_t)(i2cNSum[i2cMode]);
304  div = ((freqRef - (I2C_CR_MAX * freqScl)) / (n * freqScl)) - 1;
305  EFM_ASSERT(div >= 0);
306  EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK);
307 
308  /* Clock divisor must be at least 1 in slave mode according to reference */
309  /* manual (in which case there is normally no need to set bus frequency). */
310  if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div)
311  {
312  div = 1;
313  }
314  i2c->CLKDIV = (uint32_t)div;
315 }
316 
317 
318 /***************************************************************************/
331 void I2C_Enable(I2C_TypeDef *i2c, bool enable)
332 {
333  EFM_ASSERT(I2C_REF_VALID(i2c));
334 
335  BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable);
336 }
337 
338 
339 /***************************************************************************/
349 void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
350 {
351  EFM_ASSERT(I2C_REF_VALID(i2c));
352 
353  i2c->IEN = 0;
354  i2c->IFC = _I2C_IFC_MASK;
355 
356  /* Set SLAVE select mode */
357  BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1);
358 
359  I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr);
360 
362 }
363 
364 
365 /***************************************************************************/
377 {
378  i2c->CTRL = _I2C_CTRL_RESETVALUE;
382  i2c->IEN = _I2C_IEN_RESETVALUE;
383  i2c->IFC = _I2C_IFC_MASK;
384  /* Do not reset route register, setting should be done independently */
385 }
386 
387 
388 /***************************************************************************/
425 {
426  uint32_t tmp;
427  uint32_t pending;
428  I2C_Transfer_TypeDef *transfer;
430 
431  EFM_ASSERT(I2C_REF_VALID(i2c));
432 
433  /* Support up to 2 I2C buses */
434  if (i2c == I2C0)
435  {
436  transfer = i2cTransfer;
437  }
438 #if (I2C_COUNT > 1)
439  else if (i2c == I2C1)
440  {
441  transfer = i2cTransfer + 1;
442  }
443 #endif
444  else
445  {
446  return i2cTransferUsageFault;
447  }
448 
449  seq = transfer->seq;
450  for (;; )
451  {
452  pending = i2c->IF;
453 
454  /* If some sort of fault, abort transfer. */
455  if (pending & I2C_IF_ERRORS)
456  {
457  if (pending & I2C_IF_ARBLOST)
458  {
459  /* If arbitration fault, it indicates either a slave device */
460  /* not responding as expected, or other master which is not */
461  /* supported by this SW. */
462  transfer->result = i2cTransferArbLost;
463  }
464  else if (pending & I2C_IF_BUSERR)
465  {
466  /* A bus error indicates a misplaced start or stop, which should */
467  /* not occur in master mode controlled by this SW. */
468  transfer->result = i2cTransferBusErr;
469  }
470 
471  /* If error situation occurred, it is difficult to know */
472  /* exact cause and how to resolve. It will be up to a wrapper */
473  /* to determine how to handle a fault/recovery if possible. */
474  transfer->state = i2cStateDone;
475  goto done;
476  }
477 
478  switch (transfer->state)
479  {
480  /***************************************************/
481  /* Send first start+address (first byte if 10 bit) */
482  /***************************************************/
483  case i2cStateStartAddrSend:
484  if (seq->flags & I2C_FLAG_10BIT_ADDR)
485  {
486  tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
487 
488  /* In 10 bit address mode, the address following the first */
489  /* start always indicate write. */
490  }
491  else
492  {
493  tmp = (uint32_t)(seq->addr) & 0xfe;
494 
495  if (seq->flags & I2C_FLAG_READ)
496  {
497  /* Indicate read request */
498  tmp |= 1;
499  }
500  }
501 
502  transfer->state = i2cStateAddrWFAckNack;
503  i2c->TXDATA = tmp; /* Data not transmitted until START sent */
504  i2c->CMD = I2C_CMD_START;
505  goto done;
506 
507  /*******************************************************/
508  /* Wait for ACK/NACK on address (first byte if 10 bit) */
509  /*******************************************************/
510  case i2cStateAddrWFAckNack:
511  if (pending & I2C_IF_NACK)
512  {
513  i2c->IFC = I2C_IFC_NACK;
514  transfer->result = i2cTransferNack;
515  transfer->state = i2cStateWFStopSent;
516  i2c->CMD = I2C_CMD_STOP;
517  }
518  else if (pending & I2C_IF_ACK)
519  {
520  i2c->IFC = I2C_IFC_ACK;
521 
522  /* If 10 bit address, send 2nd byte of address. */
523  if (seq->flags & I2C_FLAG_10BIT_ADDR)
524  {
525  transfer->state = i2cStateAddrWF2ndAckNack;
526  i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
527  }
528  else
529  {
530  /* Determine whether receiving or sending data */
531  if (seq->flags & I2C_FLAG_READ)
532  {
533  transfer->state = i2cStateWFData;
534  if(seq->buf[transfer->bufIndx].len==1)
535  {
536  i2c->CMD = I2C_CMD_NACK;
537  }
538  }
539  else
540  {
541  transfer->state = i2cStateDataSend;
542  continue;
543  }
544  }
545  }
546  goto done;
547 
548  /******************************************************/
549  /* Wait for ACK/NACK on second byte of 10 bit address */
550  /******************************************************/
551  case i2cStateAddrWF2ndAckNack:
552  if (pending & I2C_IF_NACK)
553  {
554  i2c->IFC = I2C_IFC_NACK;
555  transfer->result = i2cTransferNack;
556  transfer->state = i2cStateWFStopSent;
557  i2c->CMD = I2C_CMD_STOP;
558  }
559  else if (pending & I2C_IF_ACK)
560  {
561  i2c->IFC = I2C_IFC_ACK;
562 
563  /* If using plain read sequence with 10 bit address, switch to send */
564  /* repeated start. */
565  if (seq->flags & I2C_FLAG_READ)
566  {
567  transfer->state = i2cStateRStartAddrSend;
568  }
569  /* Otherwise expected to write 0 or more bytes */
570  else
571  {
572  transfer->state = i2cStateDataSend;
573  }
574  continue;
575  }
576  goto done;
577 
578  /*******************************/
579  /* Send repeated start+address */
580  /*******************************/
581  case i2cStateRStartAddrSend:
582  if (seq->flags & I2C_FLAG_10BIT_ADDR)
583  {
584  tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
585  }
586  else
587  {
588  tmp = seq->addr & 0xfe;
589  }
590 
591  /* If this is a write+read combined sequence, then read is about to start */
592  if (seq->flags & I2C_FLAG_WRITE_READ)
593  {
594  /* Indicate read request */
595  tmp |= 1;
596  }
597 
598  transfer->state = i2cStateRAddrWFAckNack;
599  /* We have to write START cmd first since repeated start, otherwise */
600  /* data would be sent first. */
601  i2c->CMD = I2C_CMD_START;
602  i2c->TXDATA = tmp;
603  goto done;
604 
605  /**********************************************************************/
606  /* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
607  /**********************************************************************/
608  case i2cStateRAddrWFAckNack:
609  if (pending & I2C_IF_NACK)
610  {
611  i2c->IFC = I2C_IFC_NACK;
612  transfer->result = i2cTransferNack;
613  transfer->state = i2cStateWFStopSent;
614  i2c->CMD = I2C_CMD_STOP;
615  }
616  else if (pending & I2C_IF_ACK)
617  {
618  i2c->IFC = I2C_IFC_ACK;
619 
620  /* Determine whether receiving or sending data */
621  if (seq->flags & I2C_FLAG_WRITE_READ)
622  {
623  transfer->state = i2cStateWFData;
624  }
625  else
626  {
627  transfer->state = i2cStateDataSend;
628  continue;
629  }
630  }
631  goto done;
632 
633  /*****************************/
634  /* Send a data byte to slave */
635  /*****************************/
636  case i2cStateDataSend:
637  /* Reached end of data buffer? */
638  if (transfer->offset >= seq->buf[transfer->bufIndx].len)
639  {
640  /* Move to next message part */
641  transfer->offset = 0;
642  transfer->bufIndx++;
643 
644  /* Send repeated start when switching to read mode on 2nd buffer */
645  if (seq->flags & I2C_FLAG_WRITE_READ)
646  {
647  transfer->state = i2cStateRStartAddrSend;
648  continue;
649  }
650 
651  /* Only writing from one buffer, or finished both buffers */
652  if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1))
653  {
654  transfer->state = i2cStateWFStopSent;
655  i2c->CMD = I2C_CMD_STOP;
656  goto done;
657  }
658 
659  /* Reprocess in case next buffer is empty */
660  continue;
661  }
662 
663  /* Send byte */
664  i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
665  transfer->state = i2cStateDataWFAckNack;
666  goto done;
667 
668  /*********************************************************/
669  /* Wait for ACK/NACK from slave after sending data to it */
670  /*********************************************************/
671  case i2cStateDataWFAckNack:
672  if (pending & I2C_IF_NACK)
673  {
674  i2c->IFC = I2C_IFC_NACK;
675  transfer->result = i2cTransferNack;
676  transfer->state = i2cStateWFStopSent;
677  i2c->CMD = I2C_CMD_STOP;
678  }
679  else if (pending & I2C_IF_ACK)
680  {
681  i2c->IFC = I2C_IFC_ACK;
682  transfer->state = i2cStateDataSend;
683  continue;
684  }
685  goto done;
686 
687  /****************************/
688  /* Wait for data from slave */
689  /****************************/
690  case i2cStateWFData:
691  if (pending & I2C_IF_RXDATAV)
692  {
693  uint8_t data;
694  unsigned int rxLen = seq->buf[transfer->bufIndx].len;
695 
696  /* Must read out data in order to not block further progress */
697  data = (uint8_t)(i2c->RXDATA);
698 
699  /* Make sure not storing beyond end of buffer just in case */
700  if (transfer->offset < rxLen)
701  {
702  seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
703  }
704 
705  /* If we have read all requested data, then the sequence should end */
706  if (transfer->offset >= rxLen)
707  {
708  /* If there is only one byte to receive we need to transmit the
709  NACK now, before the stop. */
710  if (1 == rxLen)
711  {
712  i2c->CMD = I2C_CMD_NACK;
713  }
714 
715  transfer->state = i2cStateWFStopSent;
716  i2c->CMD = I2C_CMD_STOP;
717  }
718  else
719  {
720  /* Send ACK and wait for next byte */
721  i2c->CMD = I2C_CMD_ACK;
722 
723  if ( (1<rxLen) && (transfer->offset == (rxLen-1)) )
724  {
725  /* If there is more than one byte to receive and this is the next
726  to last byte we need to transmit the NACK now, before receiving
727  the last byte. */
728  i2c->CMD = I2C_CMD_NACK;
729  }
730  }
731  }
732  goto done;
733 
734  /***********************************/
735  /* Wait for STOP to have been sent */
736  /***********************************/
737  case i2cStateWFStopSent:
738  if (pending & I2C_IF_MSTOP)
739  {
740  i2c->IFC = I2C_IFC_MSTOP;
741  transfer->state = i2cStateDone;
742  }
743  goto done;
744 
745  /******************************/
746  /* Unexpected state, SW fault */
747  /******************************/
748  default:
749  transfer->result = i2cTransferSwFault;
750  transfer->state = i2cStateDone;
751  goto done;
752  }
753  }
754 
755  done:
756 
757  if (transfer->state == i2cStateDone)
758  {
759  /* Disable interrupt sources when done */
760  i2c->IEN = 0;
761 
762  /* Update result unless some fault already occurred */
763  if (transfer->result == i2cTransferInProgress)
764  {
765  transfer->result = i2cTransferDone;
766  }
767  }
768  /* Until transfer is done keep returning i2cTransferInProgress */
769  else
770  {
771  return i2cTransferInProgress;
772  }
773 
774  return transfer->result;
775 }
776 
777 
778 /***************************************************************************/
805 {
806  I2C_Transfer_TypeDef *transfer;
807 
808  EFM_ASSERT(I2C_REF_VALID(i2c));
809  EFM_ASSERT(seq);
810 
811  /* Support up to 2 I2C buses */
812  if (i2c == I2C0)
813  {
814  transfer = i2cTransfer;
815  }
816 #if (I2C_COUNT > 1)
817  else if (i2c == I2C1)
818  {
819  transfer = i2cTransfer + 1;
820  }
821 #endif
822  else
823  {
824  return i2cTransferUsageFault;
825  }
826 
827  /* Check if in busy state. Since this SW assumes single master, we can */
828  /* just issue an abort. The BUSY state is normal after a reset. */
829  if (i2c->STATE & I2C_STATE_BUSY)
830  {
831  i2c->CMD = I2C_CMD_ABORT;
832  }
833 
834  /* Make sure user is not trying to read 0 bytes, it is not */
835  /* possible according to I2C spec, since slave will always start */
836  /* sending first byte ACK on address. The read operation can */
837  /* only be stopped by NACKing a received byte, ie minimum 1 byte. */
838  if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) ||
839  ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
840  )
841  {
842  return i2cTransferUsageFault;
843  }
844 
845  /* Prepare for a transfer */
846  transfer->state = i2cStateStartAddrSend;
847  transfer->result = i2cTransferInProgress;
848  transfer->offset = 0;
849  transfer->bufIndx = 0;
850  transfer->seq = seq;
851 
852  /* Ensure buffers are empty */
854  if (i2c->IF & I2C_IF_RXDATAV)
855  {
856  (void)i2c->RXDATA;
857  }
858 
859  /* Clear all pending interrupts prior to starting transfer. */
860  i2c->IFC = _I2C_IFC_MASK;
861 
862  /* Enable those interrupts we are interested in throughout transfer. */
863  /* Notice that the I2C interrupt must also be enabled in the NVIC, but */
864  /* that is left for an additional driver wrapper. */
866  I2C_IF_RXDATAV | I2C_IF_ERRORS;
867 
868  /* Start transfer */
869  return I2C_Transfer(i2c);
870 }
871 
874 #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */
Clock management unit (CMU) API.
#define _I2C_CTRL_CLHR_SHIFT
__I uint32_t IF
Definition: efm32pg1b_i2c.h:56
#define I2C_IFC_NACK
Emlib peripheral API "assert" implementation.
__I uint32_t STATE
Definition: efm32pg1b_i2c.h:45
#define I2C_FLAG_READ
Indicate plain read sequence: S+ADDR(R)+DATA0+P.
Definition: em_i2c.h:130
RAM and peripheral bit-field set and clear API.
__I uint32_t RXDATA
Definition: efm32pg1b_i2c.h:50
I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq)
Prepare and start an I2C transfer (single master mode only).
Definition: em_i2c.c:803
#define I2C_IF_RXDATAV
#define I2C0
#define I2C_IF_NACK
#define I2C_IF_ARBLOST
void I2C_Enable(I2C_TypeDef *i2c, bool enable)
Enable/disable I2C.
Definition: em_i2c.c:331
#define I2C_IFC_ACK
#define _I2C_CLKDIV_RESETVALUE
#define I2C_CMD_START
#define I2C_CMD_STOP
#define _I2C_CTRL_CLHR_MASK
#define I2C_FLAG_WRITE
Indicate plain write sequence: S+ADDR(W)+DATA0+P.
Definition: em_i2c.h:119
I2C_TransferReturn_TypeDef
Definition: em_i2c.h:174
#define I2C_CMD_NACK
#define I2C_IF_MSTOP
#define _I2C_CTRL_EN_SHIFT
Definition: efm32pg1b_i2c.h:73
#define I2C_FLAG_10BIT_ADDR
Definition: em_i2c.h:157
void I2C_Reset(I2C_TypeDef *i2c)
Reset I2C to same state as after a HW reset.
Definition: em_i2c.c:376
__IO uint32_t IEN
Definition: efm32pg1b_i2c.h:59
#define _I2C_IFC_MASK
I2C_ClockHLR_TypeDef clhr
Definition: em_i2c.h:218
void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
Initialize I2C.
Definition: em_i2c.c:349
#define I2C_IF_ACK
__IO uint32_t CMD
Definition: efm32pg1b_i2c.h:44
#define I2C_CMD_ABORT
#define _I2C_CTRL_SLAVE_SHIFT
Definition: efm32pg1b_i2c.h:78
#define _I2C_SADDR_RESETVALUE
struct I2C_TransferSeq_TypeDef::@0 buf[2]
uint32_t freq
Definition: em_i2c.h:215
void I2C_BusFreqSet(I2C_TypeDef *i2c, uint32_t freqRef, uint32_t freqScl, I2C_ClockHLR_TypeDef i2cMode)
Set I2C bus frequency.
Definition: em_i2c.c:223
__IO uint32_t TXDATA
Definition: efm32pg1b_i2c.h:54
__IO uint32_t CTRL
Definition: efm32pg1b_i2c.h:43
Master mode transfer message structure used to define a complete I2C transfer sequence (from start to...
Definition: em_i2c.h:247
uint32_t refFreq
Definition: em_i2c.h:209
#define I2C_COUNT
#define _I2C_CLKDIV_DIV_MASK
#define I2C_IFC_MSTOP
#define I2C_CMD_ACK
#define _I2C_IEN_RESETVALUE
#define I2C_CTRL_SLAVE
Definition: efm32pg1b_i2c.h:77
#define I2C_STATE_BUSY
__IO uint32_t SADDR
Definition: efm32pg1b_i2c.h:48
__IO uint32_t SADDRMASK
Definition: efm32pg1b_i2c.h:49
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
Definition: em_bus.h:283
I2C_ClockHLR_TypeDef
Definition: em_i2c.h:165
#define I2C_CMD_CLEARPC
__IO uint32_t IFC
Definition: efm32pg1b_i2c.h:58
#define I2C_FLAG_WRITE_READ
Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P.
Definition: em_i2c.h:143
__IO uint32_t CLKDIV
Definition: efm32pg1b_i2c.h:47
Inter-intergrated circuit (I2C) peripheral API.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146
#define _I2C_CTRL_RESETVALUE
Definition: efm32pg1b_i2c.h:70
#define I2C_IF_BUSERR
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
Definition: em_cmu.c:1482
uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c)
Get current configured I2C bus frequency.
Definition: em_i2c.c:170
uint16_t addr
Address to use after (repeated) start.
Definition: em_i2c.h:257
I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c)
Continue an initiated I2C transfer (single master mode only).
Definition: em_i2c.c:424
#define I2C_CMD_CLEARTX
#define _I2C_SADDRMASK_RESETVALUE