36 #if defined( EMU_PRESENT ) && ( EMU_COUNT > 0 )
55 #if (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN)
56 #error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions
58 #if (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN)
59 #error Conflict in HFXOENS and HFXOEN bitpositions
61 #if (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN)
62 #error Conflict in LFRCOENS and LFRCOEN bitpositions
64 #if (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN)
65 #error Conflict in LFXOENS and LFXOEN bitpositions
71 #if defined( _EFM32_GECKO_FAMILY )
72 #define ERRATA_FIX_EMU_E107_EN
73 #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U))
74 #define NON_WIC_INT_MASK_1 (~(0x0U))
76 #elif defined( _EFM32_TINY_FAMILY )
77 #define ERRATA_FIX_EMU_E107_EN
78 #define NON_WIC_INT_MASK_0 (~(0x001be323U))
79 #define NON_WIC_INT_MASK_1 (~(0x0U))
81 #elif defined( _EFM32_GIANT_FAMILY )
82 #define ERRATA_FIX_EMU_E107_EN
83 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
84 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
86 #elif defined( _EFM32_WONDER_FAMILY )
87 #define ERRATA_FIX_EMU_E107_EN
88 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
89 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
96 #if defined( _EFM32_HAPPY_FAMILY )
97 #define ERRATA_FIX_EMU_E108_EN
102 #if defined( _EMU_DCDCCTRL_MASK )
104 #define PWRCFG_DCDCTODVDD_VMIN 1200
105 #define PWRCFG_DCDCTODVDD_VMAX 3000
109 errataFixDcdcHsTrimSet,
110 errataFixDcdcHsLnWaitDone
111 } errataFixDcdcHs_TypeDef;
112 errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit;
129 static uint32_t cmuStatus;
130 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
131 static uint16_t cmuHfclkStatus;
133 #if defined( _EMU_DCDCCTRL_MASK )
134 static uint16_t dcdcMaxCurrent_mA;
135 static uint16_t dcdcOutput_mVout;
151 static void emuRestore(
void)
173 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
174 oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0);
176 CMU->OSCENCMD = oscEnCmd;
179 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
221 switch (cmuStatus & (CMU_STATUS_HFRCOSEL
223 | CMU_STATUS_LFRCOSEL
224 #
if defined( CMU_STATUS_USHFRCODIV2SEL )
225 | CMU_STATUS_USHFRCODIV2SEL
227 | CMU_STATUS_LFXOSEL))
229 case CMU_STATUS_LFRCOSEL:
233 CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO;
236 case CMU_STATUS_LFXOSEL:
240 CMU->CMD = CMU_CMD_HFCLKSEL_LFXO;
243 case CMU_STATUS_HFXOSEL:
247 CMU->CMD = CMU_CMD_HFCLKSEL_HFXO;
250 #if defined( CMU_STATUS_USHFRCODIV2SEL )
251 case CMU_STATUS_USHFRCODIV2SEL:
253 while (!(
CMU->STATUS & CMU_STATUS_USHFRCORDY))
255 CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2;
280 #if defined( ERRATA_FIX_EMU_E107_EN )
282 static __INLINE
bool getErrataFixEmuE107En(
void)
287 uint16_t majorMinorRev;
301 #if defined( _EFM32_GECKO_FAMILY )
302 return (majorMinorRev <= 0x0103);
303 #elif defined( _EFM32_TINY_FAMILY )
304 return (majorMinorRev <= 0x0102);
305 #elif defined( _EFM32_GIANT_FAMILY )
306 return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204);
307 #elif defined( _EFM32_WONDER_FAMILY )
308 return (majorMinorRev == 0x0100);
317 #if defined( _EMU_DCDCCTRL_MASK )
319 static void maxCurrentUpdate(
void);
320 #define DCDC_LP_PFET_CNT 7
321 #define DCDC_LP_NFET_CNT 15
322 void dcdcFetCntSet(
bool lpModeSet)
325 static uint32_t emuDcdcMiscCtrlReg;
329 emuDcdcMiscCtrlReg =
EMU->DCDCMISCCTRL;
330 tmp =
EMU->DCDCMISCCTRL
334 EMU->DCDCMISCCTRL = tmp;
339 EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg;
344 void dcdcHsFixLnBlock(
void)
346 #define EMU_DCDCSTATUS (* (volatile uint32_t *)(EMU_BASE + 0x7C))
347 if (errataFixDcdcHsState == errataFixDcdcHsTrimSet)
352 while (!(EMU_DCDCSTATUS & (0x1 << 16)));
354 errataFixDcdcHsState = errataFixDcdcHsLnWaitDone;
415 #if defined( ERRATA_FIX_EMU_E107_EN )
416 bool errataFixEmuE107En;
417 uint32_t nonWicIntEn[2];
422 cmuStatus =
CMU->STATUS;
423 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
424 cmuHfclkStatus = (uint16_t)(
CMU->HFCLKSTATUS);
428 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
432 #if defined( ERRATA_FIX_EMU_E107_EN )
433 errataFixEmuE107En = getErrataFixEmuE107En();
434 if (errataFixEmuE107En)
436 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
437 NVIC->ICER[0] = nonWicIntEn[0];
438 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
439 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
440 NVIC->ICER[1] = nonWicIntEn[1];
445 #if defined( _EMU_DCDCCTRL_MASK )
452 #if defined( _EMU_DCDCCTRL_MASK )
453 dcdcFetCntSet(
false);
457 #if defined( ERRATA_FIX_EMU_E107_EN )
458 if (errataFixEmuE107En)
460 NVIC->ISER[0] = nonWicIntEn[0];
461 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
462 NVIC->ISER[1] = nonWicIntEn[1];
475 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
476 else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
479 else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))
533 #if defined( ERRATA_FIX_EMU_E107_EN )
534 bool errataFixEmuE107En;
535 uint32_t nonWicIntEn[2];
540 cmuStatus =
CMU->STATUS;
541 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
542 cmuHfclkStatus = (uint16_t)(
CMU->HFCLKSTATUS);
559 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
563 #if defined( ERRATA_FIX_EMU_E107_EN )
564 errataFixEmuE107En = getErrataFixEmuE107En();
565 if (errataFixEmuE107En)
567 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
568 NVIC->ICER[0] = nonWicIntEn[0];
569 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
570 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
571 NVIC->ICER[1] = nonWicIntEn[1];
577 #if defined( _EMU_DCDCCTRL_MASK )
584 #if defined( _EMU_DCDCCTRL_MASK )
585 dcdcFetCntSet(
false);
589 #if defined( ERRATA_FIX_EMU_E107_EN )
590 if (errataFixEmuE107En)
592 NVIC->ISER[0] = nonWicIntEn[0];
593 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
594 NVIC->ISER[1] = nonWicIntEn[1];
607 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
608 else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
611 else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))
630 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
636 uint32_t em4seq2 = (
EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)
637 | (2 << _EMU_CTRL_EM4CTRL_SHIFT);
638 uint32_t em4seq3 = (
EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)
639 | (3 << _EMU_CTRL_EM4CTRL_SHIFT);
645 #if defined( ERRATA_FIX_EMU_E108_EN )
648 *(
volatile uint32_t *)0x400C80E4 = 0;
651 #if defined( _EMU_DCDCCTRL_MASK )
656 for (i = 0; i < 4; i++)
658 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
659 EMU->EM4CTRL = em4seq2;
660 EMU->EM4CTRL = em4seq3;
662 EMU->EM4CTRL = em4seq2;
689 #if defined( _EMU_MEMCTRL_POWERDOWN_MASK )
690 EFM_ASSERT(blocks <= (_EMU_MEMCTRL_POWERDOWN_MASK
691 >> _EMU_MEMCTRL_POWERDOWN_SHIFT));
692 EMU->MEMCTRL = blocks;
694 #elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) \
695 && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK ) \
696 && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK )
697 EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK
698 | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK
699 | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK))
701 EMU->MEMCTRL = blocks;
703 #elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK )
704 EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks);
705 EMU->MEMCTRL = blocks;
707 #elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK )
709 EMU->RAM0CTRL = blocks;
739 cmuStatus =
CMU->STATUS;
740 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
741 cmuHfclkStatus = (uint16_t)(
CMU->HFCLKSTATUS);
755 #if defined( _EMU_CTRL_EMVREG_MASK )
757 : (
EMU->CTRL & ~EMU_CTRL_EMVREG);
758 #elif defined( _EMU_CTRL_EM23VREG_MASK )
760 : (
EMU->CTRL & ~EMU_CTRL_EM23VREG);
767 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
777 #if defined( _EMU_EM4CONF_MASK )
779 uint32_t em4conf =
EMU->EM4CONF;
782 em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK
783 | _EMU_EM4CONF_OSC_MASK
784 | _EMU_EM4CONF_BURTCWU_MASK
785 | _EMU_EM4CONF_VREGEN_MASK);
788 em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)
790 | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)
791 | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT);
794 EMU->EM4CONF = em4conf;
796 #elif defined( _EMU_EM4CTRL_MASK )
799 uint32_t em4ctrl =
EMU->EM4CTRL;
813 EMU->EM4CTRL = em4ctrl;
819 #if defined( BU_PRESENT )
827 void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
832 reg =
EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK
833 | _EMU_PWRCONF_VOUTSTRONG_MASK
834 | _EMU_PWRCONF_VOUTMED_MASK
835 | _EMU_PWRCONF_VOUTWEAK_MASK);
837 reg |= bupdInit->resistor
838 | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)
839 | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)
840 | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT);
845 reg =
EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
846 reg |= (bupdInit->inactivePower);
850 reg =
EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK);
851 reg |= (bupdInit->activePower);
855 reg =
EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK
856 | _EMU_BUCTRL_BODCAL_MASK
857 | _EMU_BUCTRL_STATEN_MASK
858 | _EMU_BUCTRL_EN_MASK);
862 reg |= bupdInit->probe
863 | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)
864 | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)
865 | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT);
871 EMU_BUPinEnable(bupdInit->enable);
889 EFM_ASSERT(value<=(_EMU_BUACT_BUEXTHRES_MASK>>_EMU_BUACT_BUEXTHRES_SHIFT));
894 EMU->BUACT = (
EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK)
895 | (value<<_EMU_BUACT_BUEXTHRES_SHIFT);
898 EMU->BUINACT = (
EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK)
899 | (value<<_EMU_BUINACT_BUENTHRES_SHIFT);
915 EFM_ASSERT(value < 4);
916 EFM_ASSERT(value<=(_EMU_BUACT_BUEXRANGE_MASK>>_EMU_BUACT_BUEXRANGE_SHIFT));
921 EMU->BUACT = (
EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK)
922 | (value<<_EMU_BUACT_BUEXRANGE_SHIFT);
925 EMU->BUINACT = (
EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK)
926 | (value<<_EMU_BUINACT_BUENRANGE_SHIFT);
933 #if defined( _EMU_DCDCCTRL_MASK )
945 static bool ConstCalibrationLoad(
void)
948 volatile uint32_t *reg;
951 volatile uint32_t*
const diCal_EMU_DCDCLNFREQCTRL = (
volatile uint32_t *)(0x0FE08038);
952 volatile uint32_t*
const diCal_EMU_DCDCLNVCTRL = (
volatile uint32_t *)(0x0FE08040);
953 volatile uint32_t*
const diCal_EMU_DCDCLPCTRL = (
volatile uint32_t *)(0x0FE08048);
954 volatile uint32_t*
const diCal_EMU_DCDCLPVCTRL = (
volatile uint32_t *)(0x0FE08050);
955 volatile uint32_t*
const diCal_EMU_DCDCTRIM0 = (
volatile uint32_t *)(0x0FE08058);
956 volatile uint32_t*
const diCal_EMU_DCDCTRIM1 = (
volatile uint32_t *)(0x0FE08060);
958 if (
DEVINFO->DCDCLPVCTRL0 != UINT_MAX)
960 val = *(diCal_EMU_DCDCLNFREQCTRL + 1);
961 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL;
964 val = *(diCal_EMU_DCDCLNVCTRL + 1);
965 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL;
968 val = *(diCal_EMU_DCDCLPCTRL + 1);
969 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLPCTRL;
972 val = *(diCal_EMU_DCDCLPVCTRL + 1);
973 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL;
976 val = *(diCal_EMU_DCDCTRIM0 + 1);
977 reg = (
volatile uint32_t *)*diCal_EMU_DCDCTRIM0;
980 val = *(diCal_EMU_DCDCTRIM1 + 1);
981 reg = (
volatile uint32_t *)*diCal_EMU_DCDCTRIM1;
997 void ValidatedConfigSet(
void)
999 #define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44))
1001 uint32_t dcdcTiming;
1009 #if defined( _EFR_DEVICE )
1028 && (errataFixDcdcHsState == errataFixDcdcHsInit))
1031 EMU_DCDCSMCTRL |= 1;
1033 dcdcTiming =
EMU->DCDCTIMING;
1041 EMU->DCDCTIMING = dcdcTiming;
1043 errataFixDcdcHsState = errataFixDcdcHsTrimSet;
1053 static void maxCurrentUpdate(
void)
1055 uint32_t lncLimImSel;
1056 uint32_t lpcLimImSel;
1064 lncLimImSel = (dcdcMaxCurrent_mA / (5 * (pFetCnt + 1))) - 1;
1066 lpcLimImSel = (80 / (5 * (pFetCnt + 1))) - 1;
1072 | (lncLimImSel | lpcLimImSel);
1084 static void maxCurrentSet(uint32_t mAmaxCurrent)
1086 dcdcMaxCurrent_mA = mAmaxCurrent;
1101 static bool LpCmpHystCalibrationLoad(
bool lpAttenuation, uint32_t lpCmpBias)
1104 uint32_t lpcmpHystSel;
1112 lpcmpHystSel =
DEVINFO->DCDCLPCMPHYSSEL0;
1129 lpcmpHystSel =
DEVINFO->DCDCLPCMPHYSSEL1;
1206 uint32_t lpCmpBiasSel;
1224 ConstCalibrationLoad();
1249 | ((uint32_t)lpCmpBiasSel
1253 ValidatedConfigSet();
1262 dcdcOutput_mVout = dcdcInit->
mVout;
1295 #if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK )
1297 bool validOutVoltage;
1301 uint32_t vrefLow = 0;
1302 uint32_t vrefHigh = 0;
1303 uint32_t vrefVal = 0;
1305 uint32_t mVhigh = 0;
1308 volatile uint32_t* ctrlReg;
1312 validOutVoltage =
false;
1315 validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN)
1316 && (mV <= PWRCFG_DCDCTODVDD_VMAX));
1319 if (!validOutVoltage)
1327 for (lnMode = 0; lnMode <= 1; lnMode++)
1329 if (((lnMode == 0) && !setLpVoltage)
1330 || ((lnMode == 1) && !setLnVoltage))
1335 ctrlReg = (lnMode ? &
EMU->DCDCLNVCTRL : &
EMU->DCDCLPVCTRL);
1340 attSet = (mV > 1800);
1360 vrefLow =
DEVINFO->DCDCLNVCTRL0;
1368 vrefLow =
DEVINFO->DCDCLNVCTRL0;
1382 switch (attMask | lpcmpBias)
1385 vrefLow =
DEVINFO->DCDCLPVCTRL2;
1393 vrefLow =
DEVINFO->DCDCLPVCTRL2;
1401 vrefLow =
DEVINFO->DCDCLPVCTRL3;
1409 vrefLow =
DEVINFO->DCDCLPVCTRL3;
1417 vrefLow =
DEVINFO->DCDCLPVCTRL0;
1425 vrefLow =
DEVINFO->DCDCLPVCTRL0;
1433 vrefLow =
DEVINFO->DCDCLPVCTRL1;
1441 vrefLow =
DEVINFO->DCDCLPVCTRL1;
1464 if ((vrefLow == 0xFF) && (vrefHigh == 0xFF))
1472 vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow)) / (mVhigh - mVlow);
1476 if ((vrefVal > vrefHigh) || (vrefVal < vrefLow))
1484 *ctrlReg = (vrefVal << vrefShift) | attMask;
1501 uint32_t sliceCount = 0;
1508 if (mAEm0LoadCurrent < 20)
1512 else if ((mAEm0LoadCurrent >= 20) && (mAEm0LoadCurrent < 40))
1523 if (mAEm0LoadCurrent < 10)
1527 else if ((mAEm0LoadCurrent >= 10) && (mAEm0LoadCurrent < 20))
1538 if (mAEm0LoadCurrent < 40)
1612 #if defined( EMU_STATUS_VMONRDY )
1614 __STATIC_INLINE uint32_t vmonMilliVoltToCoarseThreshold(
int mV)
1616 return (mV - 1200) / 200;
1619 __STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(
int mV, uint32_t coarseThreshold)
1621 return (mV - 1200 - (coarseThreshold * 200)) / 20;
1639 uint32_t thresholdCoarse, thresholdFine;
1642 thresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->
threshold);
1643 thresholdFine = vmonMilliVoltToFineThreshold(vmonInit->
threshold, thresholdCoarse);
1647 case emuVmonChannel_AVDD:
1656 case emuVmonChannel_ALTAVDD:
1663 case emuVmonChannel_DVDD:
1670 case emuVmonChannel_IOVDD0:
1697 uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine;
1704 riseThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->
riseThreshold);
1705 riseThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->
riseThreshold, riseThresholdCoarse);
1706 fallThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->
fallThreshold);
1707 fallThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->
fallThreshold, fallThresholdCoarse);
1711 case emuVmonChannel_AVDD:
1738 uint32_t
volatile * reg;
1743 case emuVmonChannel_AVDD:
1744 reg = &(
EMU->VMONAVDDCTRL);
1747 case emuVmonChannel_ALTAVDD:
1748 reg = &(
EMU->VMONALTAVDDCTRL);
1751 case emuVmonChannel_DVDD:
1752 reg = &(
EMU->VMONDVDDCTRL);
1755 case emuVmonChannel_IOVDD0:
1756 reg = &(
EMU->VMONIO0CTRL);
1782 case emuVmonChannel_AVDD:
1785 case emuVmonChannel_ALTAVDD:
1788 case emuVmonChannel_DVDD:
1791 case emuVmonChannel_IOVDD0:
Clock management unit (CMU) API.
#define _EMU_DCDCMISCCTRL_NFETCNT_MASK
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT
#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK
EMU_DcdcAnaPeripheralPower_TypeDef anaPeripheralPower
#define CMU_OSCENCMD_LFRCOEN
#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK
EMU_EM4PinRetention_TypeDef pinRetentionMode
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT
__STATIC_INLINE void CMU_Lock(void)
Lock the CMU in order to protect some of its registers against unintended modification.
#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT
bool EMU_DCDCPowerOff(void)
Power off the DCDC regulator.
#define _EMU_EM4CTRL_RETAINLFRCO_MASK
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK
#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT
#define CMU_STATUS_HFXORDY
bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit)
Configure DCDC regulator.
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT
#define _EMU_VMONDVDDCTRL_EN_SHIFT
#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2
#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT
#define EMU_VMONIO0CTRL_RETDIS
Emlib peripheral API "assert" implementation.
#define _EMU_STATUS_VMONALTAVDD_SHIFT
void EMU_EnterEM4(void)
Enter energy mode 4 (EM4).
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK
#define CMU_OSCENCMD_AUXHFRCOEN
void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
Get chip major/minor revision.
#define _ROMTABLE_PID0_REVMAJOR_SHIFT
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT
#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT
void EMU_MemPwrDown(uint32_t blocks)
Power down memory block.
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK
#define _ROMTABLE_PID3_REVMINORLSB_MASK
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1
#define CMU_STATUS_LFXOENS
#define _EMU_PWRCFG_PWRCFG_MASK
#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK
#define _ROMTABLE_PID2_REVMINORMSB_MASK
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT
void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit)
Initialize VMON channel with hysteresis (separate rise and fall triggers).
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK
void EMU_EnterEM3(bool restore)
Enter energy mode 3 (EM3).
void EMU_EnterEM2(bool restore)
Enter energy mode 2 (EM2).
EMU_PowerConfig_TypeDef powerConfig
bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage)
Set DCDC output voltage.
#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT
#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT
#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK
void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable)
Enable or disable a VMON channel.
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT
#define _EMU_STATUS_VMONDVDD_SHIFT
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
#define EMU_VMONIO0CTRL_RISEWU
#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT
#define _EMU_DCDCTIMING_BYPWAIT_MASK
#define _EMU_VMONAVDDCTRL_EN_SHIFT
#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT
uint16_t em01LoadCurrent_mA
#define CMU_HFCLKSTATUS_SELECTED_LFRCO
#define _EMU_VMONIO0CTRL_EN_SHIFT
#define CMU_STATUS_HFRCOENS
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT
#define EMU_PWRCFG_PWRCFG_DCDCTODVDD
void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit)
Initialize VMON channel.
#define EMU_VMONALTAVDDCTRL_RISEWU
#define EMU_VMONAVDDCTRL_RISEWU
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT
#define _EMU_DCDCTIMING_BYPWAIT_SHIFT
uint16_t em234LoadCurrent_uA
#define CMU_HFCLKSTATUS_SELECTED_HFXO
#define CMU_OSCENCMD_HFXOEN
#define EMU_VMONDVDDCTRL_RISEWU
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT
#define EMU_VMONIO0CTRL_EN
#define CMU_STATUS_HFXOENS
#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK
__STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
Get family identifier of the MCU.
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT
#define _EMU_DCDCMISCCTRL_PFETCNT_MASK
void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent)
Optimize DCDC slice count based on the estimated average load current in EM0.
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT
#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK
#define _EMU_DCDCTIMING_LNWAIT_SHIFT
#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT
#define _EMU_EM4CTRL_EM4STATE_MASK
#define _EMU_STATUS_VMONAVDD_SHIFT
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT
#define CMU_OSCENCMD_LFXODIS
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT
#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT
#define EMU_VMONIO0CTRL_FALLWU
EMU_DcdcLnRcoBand_TypeDef
#define _EMU_DCDCTIMING_LPINITWAIT_SHIFT
#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3
#define CMU_STATUS_LFRCOENS
void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)
Set DCDC Low-noise RCO band.
#define CMU_HFCLKSTATUS_SELECTED_HFRCO
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK
#define EMU_DCDCLNVCTRL_LNATT
#define _EMU_DCDCTIMING_LNWAIT_MASK
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK
#define EMU_DCDCCTRL_DCDCMODE_OFF
#define _EMU_DCDCCTRL_DCDCMODE_MASK
#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT
#define _EMU_EM4CTRL_EM4IORETMODE_MASK
#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT
#define _EMU_DCDCTIMING_LPINITWAIT_MASK
void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init)
Update EMU module with Energy Mode 2 and 3 configuration.
#define _EMU_EM4CTRL_RETAINULFRCO_MASK
#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT
#define CMU_LOCK_LOCKKEY_LOCKED
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT
#define CMU_OSCENCMD_HFRCOEN
#define CMU_OSCENCMD_LFRCODIS
#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE
#define CMU_HFCLKSTATUS_SELECTED_LFXO
#define EMU_DCDCLPVCTRL_LPATT
#define EMU_DCDCLPCTRL_LPVREFDUTYEN
#define _EMU_STATUS_VMONIO0_SHIFT
__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void)
Get DEVINFO revision.
#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1
#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT
#define EMU_VMONAVDDCTRL_FALLWU
#define EMU_VMONALTAVDDCTRL_FALLWU
#define EMU_DCDCSYNC_DCDCCTRLBUSY
#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT
#define EMU_EM4CTRL_RETAINULFRCO
#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK
#define EMU_EM4CTRL_EM4STATE_EM4H
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT
Energy management unit (EMU) peripheral API.
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT
bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel)
Get the status of a voltage monitor channel.
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK
#define CMU_HFCLKSEL_HF_LFXO
void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
Set DCDC regulator operating mode.
#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0
#define _ROMTABLE_PID0_REVMAJOR_MASK
#define CMU_HFCLKSEL_HF_HFXO
EMU_VmonChannel_TypeDef channel
EMU_DcdcMode_TypeDef dcdcMode
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT
static __INLINE void SystemCoreClockUpdate(void)
Update CMSIS SystemCoreClock variable.
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK
#define CMU_STATUS_LFXORDY
#define CMU_STATUS_LFRCORDY
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT
#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT
#define _EMU_EM4CTRL_EM4ENTRY_SHIFT
#define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK
#define EMU_VMONAVDDCTRL_EN
#define _EMU_PWRCTRL_ANASW_SHIFT
EMU_VmonChannel_TypeDef channel
#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK
void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init)
Update EMU module with Energy Mode 4 configuration.
#define EMU_VMONDVDDCTRL_EN
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK
#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK
EMU_EM4State_TypeDef em4State
#define CMU_OSCENCMD_HFRCODIS
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK
#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK
#define EMU_VMONALTAVDDCTRL_EN
#define EMU_EM4CTRL_RETAINLFRCO
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK
#define _CMU_HFCLKSTATUS_SELECTED_MASK
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT
#define CMU_OSCENCMD_LFXOEN
#define EMU_VMONDVDDCTRL_FALLWU
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK
__STATIC_INLINE void CMU_Unlock(void)
Unlock the CMU so that writing to locked registers again is possible.
#define EMU_EM4CTRL_RETAINLFXO
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK
#define CMU_HFCLKSEL_HF_LFRCO
#define _EMU_VMONALTAVDDCTRL_EN_SHIFT
#define _EMU_DCDCTIMING_DUTYSCALE_MASK
#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT
#define CMU_STATUS_AUXHFRCOENS
SYSTEM_PartFamily_TypeDef
#define _EMU_EM4CTRL_EM4ENTRY_MASK
EMU_DcdcLnTransientMode_TypeDef lnTransientMode
#define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK
#define _EMU_EM4CTRL_RETAINLFXO_MASK