EFM32 Pearl Gecko Software Documentation  efm32pg1-doc-4.2.1
em_gpio.h
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1 /***************************************************************************/
34 #ifndef __SILICON_LABS_EM_GPIO_H__
35 #define __SILICON_LABS_EM_GPIO_H__
36 
37 #include "em_device.h"
38 #if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
39 
40 #include <stdbool.h>
41 #include "em_bus.h"
42 #include "em_assert.h"
43 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
48 /***************************************************************************/
53 /***************************************************************************/
58 /*******************************************************************************
59  ******************************* DEFINES ***********************************
60  ******************************************************************************/
61 
63 #if defined( _EFM32_TINY_FAMILY ) || defined( _EFM32_ZERO_FAMILY )
64 
65 #define _GPIO_PORT_A_PIN_COUNT 14
66 #define _GPIO_PORT_B_PIN_COUNT 10
67 #define _GPIO_PORT_C_PIN_COUNT 16
68 #define _GPIO_PORT_D_PIN_COUNT 9
69 #define _GPIO_PORT_E_PIN_COUNT 12
70 #define _GPIO_PORT_F_PIN_COUNT 6
71 
72 #define _GPIO_PORT_A_PIN_MASK 0xF77F
73 #define _GPIO_PORT_B_PIN_MASK 0x79F8
74 #define _GPIO_PORT_C_PIN_MASK 0xFFFF
75 #define _GPIO_PORT_D_PIN_MASK 0x01FF
76 #define _GPIO_PORT_E_PIN_MASK 0xFFF0
77 #define _GPIO_PORT_F_PIN_MASK 0x003F
78 
79 #elif defined( _EFM32_HAPPY_FAMILY )
80 
81 #define _GPIO_PORT_A_PIN_COUNT 6
82 #define _GPIO_PORT_B_PIN_COUNT 5
83 #define _GPIO_PORT_C_PIN_COUNT 12
84 #define _GPIO_PORT_D_PIN_COUNT 4
85 #define _GPIO_PORT_E_PIN_COUNT 4
86 #define _GPIO_PORT_F_PIN_COUNT 6
87 
88 #define _GPIO_PORT_A_PIN_MASK 0x0707
89 #define _GPIO_PORT_B_PIN_MASK 0x6980
90 #define _GPIO_PORT_C_PIN_MASK 0xEF1F
91 #define _GPIO_PORT_D_PIN_MASK 0x00F0
92 #define _GPIO_PORT_E_PIN_MASK 0x3C00
93 #define _GPIO_PORT_F_PIN_MASK 0x003F
94 
95 #elif defined( _EFM32_GIANT_FAMILY ) \
96  || defined( _EFM32_WONDER_FAMILY )
97 
98 #define _GPIO_PORT_A_PIN_COUNT 16
99 #define _GPIO_PORT_B_PIN_COUNT 16
100 #define _GPIO_PORT_C_PIN_COUNT 16
101 #define _GPIO_PORT_D_PIN_COUNT 16
102 #define _GPIO_PORT_E_PIN_COUNT 16
103 #define _GPIO_PORT_F_PIN_COUNT 13
104 
105 #define _GPIO_PORT_A_PIN_MASK 0xFFFF
106 #define _GPIO_PORT_B_PIN_MASK 0xFFFF
107 #define _GPIO_PORT_C_PIN_MASK 0xFFFF
108 #define _GPIO_PORT_D_PIN_MASK 0xFFFF
109 #define _GPIO_PORT_E_PIN_MASK 0xFFFF
110 #define _GPIO_PORT_F_PIN_MASK 0x1FFF
111 
112 #elif defined( _EFM32_GECKO_FAMILY )
113 
114 #define _GPIO_PORT_A_PIN_COUNT 16
115 #define _GPIO_PORT_B_PIN_COUNT 16
116 #define _GPIO_PORT_C_PIN_COUNT 16
117 #define _GPIO_PORT_D_PIN_COUNT 16
118 #define _GPIO_PORT_E_PIN_COUNT 16
119 #define _GPIO_PORT_F_PIN_COUNT 10
120 
121 #define _GPIO_PORT_A_PIN_MASK 0xFFFF
122 #define _GPIO_PORT_B_PIN_MASK 0xFFFF
123 #define _GPIO_PORT_C_PIN_MASK 0xFFFF
124 #define _GPIO_PORT_D_PIN_MASK 0xFFFF
125 #define _GPIO_PORT_E_PIN_MASK 0xFFFF
126 #define _GPIO_PORT_F_PIN_MASK 0x03FF
127 
128 #elif defined( _EFR32_MIGHTY_FAMILY ) \
129  || defined( _EFR32_BLUE_FAMILY ) \
130  || defined( _EFR32_FLEX_FAMILY ) \
131  || defined( _EFR32_ZAPPY_FAMILY )
132 
133 #define _GPIO_PORT_A_PIN_COUNT 6
134 #define _GPIO_PORT_B_PIN_COUNT 5
135 #define _GPIO_PORT_C_PIN_COUNT 6
136 #define _GPIO_PORT_D_PIN_COUNT 3
137 #define _GPIO_PORT_E_PIN_COUNT 0
138 #define _GPIO_PORT_F_PIN_COUNT 8
139 
140 #define _GPIO_PORT_A_PIN_MASK 0x003F
141 #define _GPIO_PORT_B_PIN_MASK 0xF800
142 #define _GPIO_PORT_C_PIN_MASK 0x0FC0
143 #define _GPIO_PORT_D_PIN_MASK 0xE000
144 #define _GPIO_PORT_E_PIN_MASK 0x0000
145 #define _GPIO_PORT_F_PIN_MASK 0x00FF
146 
147 #elif defined( _EFM32_PEARL_FAMILY ) \
148  || defined( _EFM32_JADE_FAMILY )
149 
150 #define _GPIO_PORT_A_PIN_COUNT 6
151 #define _GPIO_PORT_B_PIN_COUNT 5
152 #define _GPIO_PORT_C_PIN_COUNT 6
153 #define _GPIO_PORT_D_PIN_COUNT 7
154 #define _GPIO_PORT_E_PIN_COUNT 0
155 #define _GPIO_PORT_F_PIN_COUNT 8
156 
157 #define _GPIO_PORT_A_PIN_MASK 0x003F
158 #define _GPIO_PORT_B_PIN_MASK 0xF800
159 #define _GPIO_PORT_C_PIN_MASK 0x0FC0
160 #define _GPIO_PORT_D_PIN_MASK 0xFE00
161 #define _GPIO_PORT_E_PIN_MASK 0x0000
162 #define _GPIO_PORT_F_PIN_MASK 0x00FF
163 
164 #else
165 #warning "Port and pin masks are not defined for this family."
166 #endif
167 
168 #if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )
169 #define _GPIO_PORT_SIZE(port) ( \
170  (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \
171  (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \
172  (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \
173  (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \
174  (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \
175  (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \
176  (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \
177  (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \
178  0)
179 #else
180 #define _GPIO_PORT_SIZE(port) ( \
181  (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \
182  (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \
183  (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \
184  (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \
185  (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \
186  (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \
187  0)
188 #endif
189 
190 #if defined( _GPIO_PORT_G_PIN_MASK ) && defined( _GPIO_PORT_H_PIN_MASK )
191 #define _GPIO_PORT_MASK(port) ( \
192  (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \
193  (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \
194  (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \
195  (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \
196  (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \
197  (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \
198  (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \
199  (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \
200  0)
201 #else
202 #define _GPIO_PORT_MASK(port) ( \
203  (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \
204  (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \
205  (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \
206  (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \
207  (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \
208  (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \
209  0)
210 #endif
211 
213 #define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) )
214 #define GPIO_PORT_PIN_VALID(port, pin) ((( _GPIO_PORT_MASK(port)) >> (pin)) & 0x1 )
215 
217 #define GPIO_PIN_MAX 15
218 
220 #if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )
221 #define GPIO_PORT_MAX 7
222 #else
223 #define GPIO_PORT_MAX 5
224 #endif
225 
227 /*******************************************************************************
228  ******************************** ENUMS ************************************
229  ******************************************************************************/
230 
232 typedef enum
233 {
234 #if ( _GPIO_PORT_A_PIN_COUNT > 0 )
235  gpioPortA = 0,
236 #endif
237 #if ( _GPIO_PORT_B_PIN_COUNT > 0 )
238  gpioPortB = 1,
239 #endif
240 #if ( _GPIO_PORT_C_PIN_COUNT > 0 )
241  gpioPortC = 2,
242 #endif
243 #if ( _GPIO_PORT_D_PIN_COUNT > 0 )
244  gpioPortD = 3,
245 #endif
246 #if ( _GPIO_PORT_E_PIN_COUNT > 0 )
247  gpioPortE = 4,
248 #endif
249 #if ( _GPIO_PORT_F_PIN_COUNT > 0 )
250  gpioPortF = 5
251 #endif
252 #if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 )
253  gpioPortG = 6
254 #endif
255 #if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 )
256  gpioPortH = 7
257 #endif
259 
260 #if defined( _GPIO_P_CTRL_DRIVEMODE_MASK )
261 
262 typedef enum
263 {
265  gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD,
267  gpioDriveModeLowest = GPIO_P_CTRL_DRIVEMODE_LOWEST,
269  gpioDriveModeHigh = GPIO_P_CTRL_DRIVEMODE_HIGH,
271  gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW
272 } GPIO_DriveMode_TypeDef;
273 #endif
274 
275 #if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK ) && defined( _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK )
276 
277 typedef enum
278 {
281 
284 
287 
291 /* For legacy support */
292 #define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong
293 #define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak
294 #endif
295 
298 typedef enum
299 {
310 #if defined( _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE )
311 
312  gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE,
313 #endif
314 #if defined( _GPIO_P_MODEL_MODE0_PUSHPULLALT )
315 
317 #endif
318 
330 #if defined( _GPIO_P_MODEL_MODE0_WIREDANDDRIVE )
331 
332  gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,
334  gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER,
336  gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP,
338  gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER
339 #endif
340 #if defined( _GPIO_P_MODEL_MODE0_WIREDANDALT )
341 
349 #endif
351 
352 /*******************************************************************************
353  ***************************** PROTOTYPES **********************************
354  ******************************************************************************/
355 
356 void GPIO_DbgLocationSet(unsigned int location);
357 
359  unsigned int pin,
360  bool risingEdge,
361  bool fallingEdge,
362  bool enable);
363 
365  unsigned int pin,
366  GPIO_Mode_TypeDef mode,
367  unsigned int out);
368 
369 # if defined( _GPIO_EM4WUEN_MASK )
370 void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask);
371 #endif
372 
373 /***************************************************************************/
385 __STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)
386 {
387 #if defined( _GPIO_ROUTE_SWCLKPEN_MASK )
388  BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, enable);
389 #elif defined( _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK )
391 #else
392 #warning "ROUTE enable for SWCLK pin is not defined."
393 #endif
394 }
395 
396 
397 /***************************************************************************/
409 __STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
410 {
411 #if defined( _GPIO_ROUTE_SWDIOPEN_MASK )
412  BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, enable);
413 #elif defined( _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK )
415 #else
416 #warning "ROUTE enable for SWDIO pin is not defined."
417 #endif
418 }
419 
420 
421 #if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
422 /***************************************************************************/
435 __STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)
436 {
437 #if defined( _GPIO_ROUTE_SWOPEN_MASK )
438  BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, enable);
439 #elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
440  BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, enable);
441 #else
442 #warning "ROUTE enable for SWO/SWV pin is not defined."
443 #endif
444 }
445 #endif
446 
447 #if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)
448 void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);
449 #endif
450 
451 #if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK )
453 #endif
454 
455 # if defined( _GPIO_EM4WUEN_MASK )
456 /**************************************************************************/
464 __STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask)
465 {
466  EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
467 
468  GPIO->EM4WUEN &= ~pinmask;
469 }
470 #endif
471 
472 
473 #if defined( _GPIO_EM4WUCAUSE_MASK ) || defined( _RMU_RSTCAUSE_EM4RST_MASK )
474 /**************************************************************************/
482 __STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
483 {
484 #if defined( _GPIO_EM4WUCAUSE_MASK )
485  return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK;
486 #else
487  return RMU->RSTCAUSE & _RMU_RSTCAUSE_EM4RST_MASK;
488 #endif
489 }
490 #endif
491 
492 
493 #if defined( GPIO_CTRL_EM4RET ) || defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
494 /**************************************************************************/
508 __STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable)
509 {
510  if (enable)
511  {
512 #if defined( GPIO_CTRL_EM4RET )
513  GPIO->CTRL |= GPIO_CTRL_EM4RET;
514 #else
515  EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
517 #endif
518  }
519  else
520  {
521 #if defined( GPIO_CTRL_EM4RET )
522  GPIO->CTRL &= ~GPIO_CTRL_EM4RET;
523 #else
524  EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
526 #endif
527  }
528 }
529 #endif
530 
531 
532 /***************************************************************************/
548 __STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask)
549 {
550  GPIO->INSENSE = (GPIO->INSENSE & ~mask) | (val & mask);
551 }
552 
553 
554 /***************************************************************************/
561 __STATIC_INLINE void GPIO_IntClear(uint32_t flags)
562 {
563  GPIO->IFC = flags;
564 }
565 
566 
567 /***************************************************************************/
574 __STATIC_INLINE void GPIO_IntDisable(uint32_t flags)
575 {
576  GPIO->IEN &= ~flags;
577 }
578 
579 
580 /***************************************************************************/
592 __STATIC_INLINE void GPIO_IntEnable(uint32_t flags)
593 {
594  GPIO->IEN |= flags;
595 }
596 
597 
598 /***************************************************************************/
605 __STATIC_INLINE uint32_t GPIO_IntGet(void)
606 {
607  return GPIO->IF;
608 }
609 
610 
611 /***************************************************************************/
626 __STATIC_INLINE uint32_t GPIO_IntGetEnabled(void)
627 {
628  uint32_t tmp;
629 
630  /* Store GPIO->IEN in temporary variable in order to define explicit order
631  * of volatile accesses. */
632  tmp = GPIO->IEN;
633 
634  /* Bitwise AND of pending and enabled interrupts */
635  return GPIO->IF & tmp;
636 }
637 
638 
639 /**************************************************************************/
646 __STATIC_INLINE void GPIO_IntSet(uint32_t flags)
647 {
648  GPIO->IFS = flags;
649 }
650 
651 
652 /***************************************************************************/
656 __STATIC_INLINE void GPIO_Lock(void)
657 {
659 }
660 
661 
662 /***************************************************************************/
675 __STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port,
676  unsigned int pin)
677 {
678  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
679  return BUS_RegBitRead(&GPIO->P[port].DIN, pin);
680 }
681 
682 
683 /***************************************************************************/
698 __STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
699 {
700  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
701 #if defined( _GPIO_P_DOUTCLR_MASK )
702  GPIO->P[port].DOUTCLR = 1 << pin;
703 #else
704  BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 0);
705 #endif
706 }
707 
708 
709 /***************************************************************************/
722 __STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port,
723  unsigned int pin)
724 {
725  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
726  return BUS_RegBitRead(&GPIO->P[port].DOUT, pin);
727 }
728 
729 
730 /***************************************************************************/
745 __STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
746 {
747  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
748 #if defined( _GPIO_P_DOUTSET_MASK )
749  GPIO->P[port].DOUTSET = 1 << pin;
750 #else
751  BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 1);
752 #endif
753 }
754 
755 
756 /***************************************************************************/
771 __STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin)
772 {
773  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
774 
775  GPIO->P[port].DOUTTGL = 1 << pin;
776 }
777 
778 
779 /***************************************************************************/
786 __STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port)
787 {
788  EFM_ASSERT(GPIO_PORT_VALID(port));
789 
790  return GPIO->P[port].DIN;
791 }
792 
793 
794 /***************************************************************************/
809 __STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins)
810 {
811  EFM_ASSERT(GPIO_PORT_VALID(port));
812 #if defined( _GPIO_P_DOUTCLR_MASK )
813  GPIO->P[port].DOUTCLR = pins;
814 #else
815  BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins);
816 #endif
817 }
818 
819 
820 /***************************************************************************/
830 __STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port)
831 {
832  EFM_ASSERT(GPIO_PORT_VALID(port));
833 
834  return GPIO->P[port].DOUT;
835 }
836 
837 
838 /***************************************************************************/
853 __STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins)
854 {
855  EFM_ASSERT(GPIO_PORT_VALID(port));
856 #if defined( _GPIO_P_DOUTSET_MASK )
857  GPIO->P[port].DOUTSET = pins;
858 #else
859  BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins);
860 #endif
861 }
862 
863 
864 /***************************************************************************/
882 __STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port,
883  uint32_t val,
884  uint32_t mask)
885 {
886  EFM_ASSERT(GPIO_PORT_VALID(port));
887 
888  GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask);
889 }
890 
891 
892 /***************************************************************************/
907 __STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins)
908 {
909  EFM_ASSERT(GPIO_PORT_VALID(port));
910 
911  GPIO->P[port].DOUTTGL = pins;
912 }
913 
914 
915 /***************************************************************************/
919 __STATIC_INLINE void GPIO_Unlock(void)
920 {
922 }
923 
927 #ifdef __cplusplus
928 }
929 #endif
930 
931 #endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */
932 #endif /* __SILICON_LABS_EM_GPIO_H__ */
#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP
__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)
Enable/disable serial wire clock pin.
Definition: em_gpio.h:385
__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
Check which GPIO pin(s) that caused a wake-up from EM4.
Definition: em_gpio.h:482
GPIO_Port_TypeDef
Definition: em_gpio.h:232
#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER
__STATIC_INLINE void GPIO_Unlock(void)
Unlocks the GPIO configuration.
Definition: em_gpio.h:919
Emlib peripheral API "assert" implementation.
#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP
__STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins)
Toggle pins in GPIO port data out register.
Definition: em_gpio.h:907
#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER
RAM and peripheral bit-field set and clear API.
__STATIC_INLINE uint32_t GPIO_IntGetEnabled(void)
Get enabled and pending GPIO interrupt flags. Useful for handling more interrupt sources in the same ...
Definition: em_gpio.h:626
__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin)
Toggle a single pin in GPIO port data out register.
Definition: em_gpio.h:771
__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins)
Set bits GPIO data out register to 1.
Definition: em_gpio.h:853
#define _GPIO_P_MODEL_MODE0_INPUTPULL
#define _GPIO_EM4WUEN_MASK
__STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask)
Disable GPIO pin wake-up from EM4.
Definition: em_gpio.h:464
#define _GPIO_P_MODEL_MODE0_PUSHPULLALT
__STATIC_INLINE void GPIO_IntClear(uint32_t flags)
Clear one or more pending GPIO interrupts.
Definition: em_gpio.h:561
__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins)
Set bits in DOUT register for a port to 0.
Definition: em_gpio.h:809
#define _GPIO_P_MODEL_MODE0_WIREDAND
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
#define GPIO_LOCK_LOCKKEY_UNLOCK
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
Definition: em_bus.h:185
#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG
void GPIO_DbgLocationSet(unsigned int location)
Sets the pin location of the debug pins (Serial Wire interface).
Definition: em_gpio.c:78
__STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port)
Read the pad values for GPIO port.
Definition: em_gpio.h:786
#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT
#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN
#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK
void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
Enable GPIO pin wake-up from EM4. When the function exits, EM4 mode can be safely entered...
Definition: em_gpio.c:292
#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT
GPIO_DriveStrength_TypeDef
Definition: em_gpio.h:277
__STATIC_INLINE void GPIO_IntDisable(uint32_t flags)
Disable one or more GPIO interrupts.
Definition: em_gpio.h:574
#define _GPIO_P_MODEL_MODE0_INPUT
#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER
GPIO_Mode_TypeDef
Definition: em_gpio.h:298
#define _GPIO_ROUTEPEN_SWVPEN_SHIFT
__STATIC_INLINE void GPIO_IntEnable(uint32_t flags)
Enable one or more GPIO interrupts.
Definition: em_gpio.h:592
#define EMU_EM4CTRL_EM4IORETMODE_DISABLE
#define GPIO_LOCK_LOCKKEY_LOCK
void GPIO_PinModeSet(GPIO_Port_TypeDef port, unsigned int pin, GPIO_Mode_TypeDef mode, unsigned int out)
Set the mode for a GPIO pin.
Definition: em_gpio.c:226
__STATIC_INLINE void GPIO_Lock(void)
Locks the GPIO configuration.
Definition: em_gpio.h:656
__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, uint32_t val, uint32_t mask)
Set GPIO port data out register.
Definition: em_gpio.h:882
__STATIC_INLINE void GPIO_IntSet(uint32_t flags)
Set one or more pending GPIO interrupts from SW.
Definition: em_gpio.h:646
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out register to 1.
Definition: em_gpio.h:745
#define _EMU_EM4CTRL_EM4IORETMODE_MASK
__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask)
Enable/disable input sensing.
Definition: em_gpio.h:548
#define _GPIO_P_MODEL_MODE0_WIREDOR
__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, unsigned int pin)
Get current setting for a pin in a GPIO port data out register.
Definition: em_gpio.h:722
__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, uint32_t mask)
Perform a masked set operation on peripheral register address.
Definition: em_bus.h:219
#define _GPIO_P_MODEL_MODE0_PUSHPULL
#define _RMU_RSTCAUSE_EM4RST_MASK
__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, uint32_t mask)
Perform a masked clear operation on peripheral register address.
Definition: em_bus.h:251
#define RMU
void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength)
Sets the drive strength for a GPIO port.
Definition: em_gpio.c:122
__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)
Enable/Disable serial wire output pin.
Definition: em_gpio.h:435
#define _GPIO_P_MODEL_MODE0_WIREDANDALT
__STATIC_INLINE uint32_t GPIO_IntGet(void)
Get pending GPIO interrupts.
Definition: em_gpio.h:605
#define _GPIO_P_MODEL_MODE0_DISABLED
#define EMU
#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK
#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER
#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT
#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER
__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
Enable/disable serial wire data I/O pin.
Definition: em_gpio.h:409
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
Set a single pin in GPIO data out port register to 0.
Definition: em_gpio.h:698
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146
#define GPIO
__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, unsigned int pin)
Read the pad value for a single pin in a GPIO port.
Definition: em_gpio.h:675
#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG
__STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port)
Get current setting for a GPIO port data out register.
Definition: em_gpio.h:830
void GPIO_IntConfig(GPIO_Port_TypeDef port, unsigned int pin, bool risingEdge, bool fallingEdge, bool enable)
Configure GPIO interrupt.
Definition: em_gpio.c:168
__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable)
Enable GPIO pin retention of output enable, output value, pull enable and pull direction in EM4...
Definition: em_gpio.h:508