EFM32 Pearl Gecko Software Documentation  efm32pg1-doc-4.2.1
efm32pg1b_devinfo.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __I uint32_t CAL;
44  uint32_t RESERVED0[9];
45  __I uint32_t EUI48L;
46  __I uint32_t EUI48H;
47  __I uint32_t CUSTOMINFO;
48  __I uint32_t MEMINFO;
49  uint32_t RESERVED1[2];
50  __I uint32_t UNIQUEL;
51  __I uint32_t UNIQUEH;
52  __I uint32_t MSIZE;
53  __I uint32_t PART;
54  __I uint32_t DEVINFOREV;
55  __I uint32_t EMUTEMP;
56  uint32_t RESERVED2[2];
57  __I uint32_t ADC0CAL0;
58  __I uint32_t ADC0CAL1;
59  __I uint32_t ADC0CAL2;
60  __I uint32_t ADC0CAL3;
61  uint32_t RESERVED3[4];
62  __I uint32_t HFRCOCAL0;
63  uint32_t RESERVED4[2];
64  __I uint32_t HFRCOCAL3;
65  uint32_t RESERVED5[2];
66  __I uint32_t HFRCOCAL6;
67  __I uint32_t HFRCOCAL7;
68  __I uint32_t HFRCOCAL8;
69  uint32_t RESERVED6[1];
70  __I uint32_t HFRCOCAL10;
71  __I uint32_t HFRCOCAL11;
72  __I uint32_t HFRCOCAL12;
73  uint32_t RESERVED7[11];
74  __I uint32_t AUXHFRCOCAL0;
75  uint32_t RESERVED8[2];
76  __I uint32_t AUXHFRCOCAL3;
77  uint32_t RESERVED9[2];
78  __I uint32_t AUXHFRCOCAL6;
79  __I uint32_t AUXHFRCOCAL7;
80  __I uint32_t AUXHFRCOCAL8;
81  uint32_t RESERVED10[1];
82  __I uint32_t AUXHFRCOCAL10;
83  __I uint32_t AUXHFRCOCAL11;
84  __I uint32_t AUXHFRCOCAL12;
85  uint32_t RESERVED11[11];
86  __I uint32_t VMONCAL0;
87  __I uint32_t VMONCAL1;
88  __I uint32_t VMONCAL2;
89  uint32_t RESERVED12[3];
90  __I uint32_t IDAC0CAL0;
91  __I uint32_t IDAC0CAL1;
92  uint32_t RESERVED13[2];
93  __I uint32_t DCDCLNVCTRL0;
94  __I uint32_t DCDCLPVCTRL0;
95  __I uint32_t DCDCLPVCTRL1;
96  __I uint32_t DCDCLPVCTRL2;
97  __I uint32_t DCDCLPVCTRL3;
98  __I uint32_t DCDCLPCMPHYSSEL0;
99  __I uint32_t DCDCLPCMPHYSSEL1;
100 } DEVINFO_TypeDef;
102 /**************************************************************************/
107 /* Bit fields for DEVINFO CAL */
108 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL
109 #define _DEVINFO_CAL_CRC_SHIFT 0
110 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL
111 #define _DEVINFO_CAL_TEMP_SHIFT 16
112 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL
114 /* Bit fields for DEVINFO EUI48L */
115 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL
116 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0
117 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL
118 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24
119 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL
121 /* Bit fields for DEVINFO EUI48H */
122 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL
123 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0
124 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL
126 /* Bit fields for DEVINFO CUSTOMINFO */
127 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL
128 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16
129 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL
131 /* Bit fields for DEVINFO MEMINFO */
132 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL
133 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0
134 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL
135 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL
136 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL
137 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL
138 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL
139 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)
140 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0)
141 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0)
142 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)
143 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8
144 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL
145 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL
146 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL
147 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL
148 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)
149 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8)
150 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8)
151 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16
152 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL
153 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24
154 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL
156 /* Bit fields for DEVINFO UNIQUEL */
157 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL
158 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0
159 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL
161 /* Bit fields for DEVINFO UNIQUEH */
162 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL
163 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0
164 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL
166 /* Bit fields for DEVINFO MSIZE */
167 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL
168 #define _DEVINFO_MSIZE_FLASH_SHIFT 0
169 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL
170 #define _DEVINFO_MSIZE_SRAM_SHIFT 16
171 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL
173 /* Bit fields for DEVINFO PART */
174 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL
175 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0
176 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL
177 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16
178 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL
179 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL
180 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL
181 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL
182 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL
183 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL
184 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL
185 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P 0x00000016UL
186 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B 0x00000017UL
187 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V 0x00000018UL
188 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL
189 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL
190 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL
191 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL
192 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL
193 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL
194 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL
195 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL
196 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL
197 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL
198 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL
199 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL
200 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL
201 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL
202 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL
203 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL
204 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL
205 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL
206 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL
207 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL
208 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL
209 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL
210 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16)
211 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16)
212 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16)
213 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16)
214 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16)
215 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16)
216 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P << 16)
217 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B << 16)
218 #define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V << 16)
219 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16)
220 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16)
221 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16)
222 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16)
223 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)
224 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)
225 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16)
226 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16)
227 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)
228 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)
229 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16)
230 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)
231 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16)
232 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16)
233 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)
234 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16)
235 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)
236 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16)
237 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16)
238 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)
239 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)
240 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)
241 #define _DEVINFO_PART_PROD_REV_SHIFT 24
242 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL
244 /* Bit fields for DEVINFO DEVINFOREV */
245 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL
246 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0
247 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL
249 /* Bit fields for DEVINFO EMUTEMP */
250 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL
251 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0
252 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL
254 /* Bit fields for DEVINFO ADC0CAL0 */
255 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL
256 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0
257 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL
258 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4
259 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL
260 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8
261 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL
262 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16
263 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL
264 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20
265 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL
266 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24
267 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL
269 /* Bit fields for DEVINFO ADC0CAL1 */
270 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL
271 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0
272 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL
273 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4
274 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL
275 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8
276 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL
277 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16
278 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL
279 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20
280 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL
281 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24
282 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL
284 /* Bit fields for DEVINFO ADC0CAL2 */
285 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL
286 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0
287 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL
288 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4
289 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL
291 /* Bit fields for DEVINFO ADC0CAL3 */
292 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL
293 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4
294 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL
296 /* Bit fields for DEVINFO HFRCOCAL0 */
297 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL
298 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0
299 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL
300 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8
301 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL
302 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16
303 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
304 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21
305 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL
306 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24
307 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL
308 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25
309 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL
310 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27
311 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
312 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28
313 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL
315 /* Bit fields for DEVINFO HFRCOCAL3 */
316 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL
317 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0
318 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL
319 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8
320 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL
321 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16
322 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
323 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21
324 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL
325 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24
326 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL
327 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25
328 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL
329 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27
330 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
331 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28
332 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL
334 /* Bit fields for DEVINFO HFRCOCAL6 */
335 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL
336 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0
337 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL
338 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8
339 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL
340 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16
341 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
342 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21
343 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL
344 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24
345 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL
346 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25
347 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL
348 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27
349 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
350 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28
351 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL
353 /* Bit fields for DEVINFO HFRCOCAL7 */
354 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL
355 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0
356 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL
357 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8
358 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL
359 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16
360 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
361 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21
362 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL
363 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24
364 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL
365 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25
366 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL
367 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27
368 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
369 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28
370 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL
372 /* Bit fields for DEVINFO HFRCOCAL8 */
373 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL
374 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0
375 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL
376 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8
377 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL
378 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16
379 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
380 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21
381 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL
382 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24
383 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL
384 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25
385 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL
386 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27
387 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
388 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28
389 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL
391 /* Bit fields for DEVINFO HFRCOCAL10 */
392 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL
393 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0
394 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL
395 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8
396 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL
397 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16
398 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
399 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21
400 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL
401 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24
402 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL
403 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25
404 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL
405 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27
406 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
407 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28
408 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL
410 /* Bit fields for DEVINFO HFRCOCAL11 */
411 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL
412 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0
413 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL
414 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8
415 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL
416 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16
417 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
418 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21
419 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL
420 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24
421 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL
422 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25
423 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL
424 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27
425 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
426 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28
427 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL
429 /* Bit fields for DEVINFO HFRCOCAL12 */
430 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL
431 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0
432 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL
433 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8
434 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL
435 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16
436 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
437 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21
438 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL
439 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24
440 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL
441 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25
442 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL
443 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27
444 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
445 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28
446 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL
448 /* Bit fields for DEVINFO AUXHFRCOCAL0 */
449 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL
450 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0
451 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL
452 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8
453 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL
454 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16
455 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
456 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21
457 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL
458 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24
459 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL
460 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25
461 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL
462 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27
463 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
464 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28
465 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL
467 /* Bit fields for DEVINFO AUXHFRCOCAL3 */
468 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL
469 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0
470 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL
471 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8
472 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL
473 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16
474 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
475 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21
476 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL
477 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24
478 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL
479 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25
480 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL
481 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27
482 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
483 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28
484 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL
486 /* Bit fields for DEVINFO AUXHFRCOCAL6 */
487 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL
488 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0
489 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL
490 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8
491 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL
492 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16
493 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
494 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21
495 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL
496 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24
497 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL
498 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25
499 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL
500 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27
501 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
502 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28
503 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL
505 /* Bit fields for DEVINFO AUXHFRCOCAL7 */
506 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL
507 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0
508 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL
509 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8
510 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL
511 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16
512 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
513 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21
514 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL
515 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24
516 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL
517 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25
518 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL
519 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27
520 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
521 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28
522 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL
524 /* Bit fields for DEVINFO AUXHFRCOCAL8 */
525 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL
526 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0
527 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL
528 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8
529 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL
530 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16
531 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
532 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21
533 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL
534 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24
535 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL
536 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25
537 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL
538 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27
539 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
540 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28
541 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL
543 /* Bit fields for DEVINFO AUXHFRCOCAL10 */
544 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL
545 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0
546 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL
547 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8
548 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL
549 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16
550 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
551 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21
552 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL
553 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24
554 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL
555 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25
556 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL
557 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27
558 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
559 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28
560 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL
562 /* Bit fields for DEVINFO AUXHFRCOCAL11 */
563 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL
564 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0
565 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL
566 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8
567 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL
568 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16
569 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
570 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21
571 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL
572 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24
573 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL
574 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25
575 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL
576 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27
577 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
578 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28
579 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL
581 /* Bit fields for DEVINFO AUXHFRCOCAL12 */
582 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL
583 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0
584 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL
585 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8
586 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL
587 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16
588 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
589 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21
590 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL
591 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24
592 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL
593 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25
594 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL
595 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27
596 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
597 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28
598 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL
600 /* Bit fields for DEVINFO VMONCAL0 */
601 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL
602 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0
603 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL
604 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4
605 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL
606 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8
607 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL
608 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12
609 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL
610 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16
611 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL
612 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20
613 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL
614 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24
615 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL
616 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28
617 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL
619 /* Bit fields for DEVINFO VMONCAL1 */
620 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL
621 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0
622 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL
623 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4
624 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL
625 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8
626 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL
627 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12
628 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL
629 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16
630 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL
631 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20
632 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL
633 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24
634 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL
635 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28
636 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL
638 /* Bit fields for DEVINFO VMONCAL2 */
639 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL
640 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0
641 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL
642 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4
643 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL
644 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8
645 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL
646 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12
647 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL
648 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16
649 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL
650 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20
651 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL
652 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24
653 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL
654 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28
655 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL
657 /* Bit fields for DEVINFO IDAC0CAL0 */
658 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL
659 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0
660 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL
661 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8
662 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL
663 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16
664 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL
665 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24
666 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL
668 /* Bit fields for DEVINFO IDAC0CAL1 */
669 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL
670 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0
671 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL
672 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8
673 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL
674 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16
675 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL
676 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24
677 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL
679 /* Bit fields for DEVINFO DCDCLNVCTRL0 */
680 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL
681 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0
682 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL
683 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8
684 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL
685 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16
686 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL
687 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24
688 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL
690 /* Bit fields for DEVINFO DCDCLPVCTRL0 */
691 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL
692 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0
693 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL
694 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8
695 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL
696 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16
697 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL
698 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24
699 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL
701 /* Bit fields for DEVINFO DCDCLPVCTRL1 */
702 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL
703 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0
704 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL
705 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8
706 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL
707 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16
708 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL
709 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24
710 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL
712 /* Bit fields for DEVINFO DCDCLPVCTRL2 */
713 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL
714 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0
715 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL
716 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8
717 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL
718 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16
719 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL
720 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24
721 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL
723 /* Bit fields for DEVINFO DCDCLPVCTRL3 */
724 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL
725 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0
726 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL
727 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8
728 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL
729 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16
730 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL
731 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24
732 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL
734 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
735 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL
736 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0
737 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL
738 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8
739 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL
741 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
742 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL
743 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0
744 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL
745 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8
746 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL
747 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16
748 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL
749 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24
750 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL
__I uint32_t VMONCAL1
__I uint32_t DCDCLNVCTRL0
__I uint32_t HFRCOCAL11
__I uint32_t AUXHFRCOCAL6
__I uint32_t AUXHFRCOCAL7
__I uint32_t AUXHFRCOCAL11
__I uint32_t UNIQUEL
__I uint32_t AUXHFRCOCAL3
__I uint32_t VMONCAL0
__I uint32_t DCDCLPVCTRL2
__I uint32_t EUI48L
__I uint32_t UNIQUEH
__I uint32_t ADC0CAL2
__I uint32_t ADC0CAL3
__I uint32_t EMUTEMP
__I uint32_t IDAC0CAL1
__I uint32_t DCDCLPCMPHYSSEL0
__I uint32_t ADC0CAL1
__I uint32_t IDAC0CAL0
__I uint32_t VMONCAL2
__I uint32_t HFRCOCAL10
__I uint32_t CUSTOMINFO
__I uint32_t HFRCOCAL12
__I uint32_t HFRCOCAL0
__I uint32_t HFRCOCAL7
__I uint32_t MSIZE
__I uint32_t DEVINFOREV
__I uint32_t AUXHFRCOCAL10
__I uint32_t HFRCOCAL6
__I uint32_t AUXHFRCOCAL12
__I uint32_t DCDCLPVCTRL3
__I uint32_t EUI48H
__I uint32_t DCDCLPCMPHYSSEL1
__I uint32_t HFRCOCAL8
__I uint32_t AUXHFRCOCAL8
__I uint32_t HFRCOCAL3
__I uint32_t MEMINFO
__I uint32_t CAL
__I uint32_t DCDCLPVCTRL1
__I uint32_t DCDCLPVCTRL0
__I uint32_t PART
__I uint32_t ADC0CAL0
__I uint32_t AUXHFRCOCAL0