EFM32 Pearl Gecko Software Documentation  efm32pg1-doc-4.2.1
em_pcnt.c
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1 /***************************************************************************/
33 #include "em_pcnt.h"
34 #if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
35 
36 #include "em_cmu.h"
37 #include "em_assert.h"
38 #include "em_bus.h"
39 
40 /***************************************************************************/
45 /***************************************************************************/
51 /*******************************************************************************
52  ******************************* DEFINES ***********************************
53  ******************************************************************************/
54 
59 #if (PCNT_COUNT == 1)
60 #define PCNT_REF_VALID(ref) ((ref) == PCNT0)
61 #elif (PCNT_COUNT == 2)
62 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1))
63 #elif (PCNT_COUNT == 3)
64 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) || \
65  ((ref) == PCNT2))
66 #else
67 #error "Undefined number of pulse counters (PCNT)."
68 #endif
69 
73 /*******************************************************************************
74  ************************** LOCAL FUNCTIONS ********************************
75  ******************************************************************************/
76 
79 /***************************************************************************/
89 __STATIC_INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt)
90 {
91  return ((uint32_t)pcnt - PCNT0_BASE) / 0x400;
92 }
93 
94 
95 /***************************************************************************/
106 __STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask)
107 {
108  /* Avoid deadlock if modifying the same register twice when freeze mode is
109  * activated. */
110  if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE)
111  {
112  return;
113  }
114 
115  /* Wait for any pending previous write operation to have been completed in low
116  * frequency domain. */
117  while (pcnt->SYNCBUSY & mask)
118  ;
119 }
120 
123 /*******************************************************************************
124  ************************** GLOBAL FUNCTIONS *******************************
125  ******************************************************************************/
126 
127 /***************************************************************************/
142 {
143  EFM_ASSERT(PCNT_REF_VALID(pcnt));
144 
145  /* Enable reset of CNT and TOP register */
147 
148  /* Disable reset of CNT and TOP register */
150 }
151 
152 
153 /***************************************************************************/
177 void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
178 {
179  uint32_t ctrl;
180 
181  EFM_ASSERT(PCNT_REF_VALID(pcnt));
182 
183 #ifdef PCNT0
184  if (PCNT0 == pcnt)
185  {
186  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > count);
187  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > top);
188  }
189 #endif
190 
191 #ifdef PCNT1
192  if (PCNT1 == pcnt)
193  {
194  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > count);
195  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > top);
196  }
197 #endif
198 
199 #ifdef PCNT2
200  if (PCNT2 == pcnt)
201  {
202  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > count);
203  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > top);
204  }
205 #endif
206 
207  /* Keep current control setting, must be restored */
208  ctrl = pcnt->CTRL;
209 
210  /* If enabled, disable pulse counter before changing values */
212  {
213  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
214  pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE;
215  }
216 
217  /* Load into TOPB */
218  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
219  pcnt->TOPB = count;
220 
221  /* Load TOPB value into TOP */
222  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
223 
224  /* This bit has no effect on rev. C and onwards parts - for compatibility */
225  pcnt->CMD = PCNT_CMD_LTOPBIM;
226  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
227 
228  /* Load TOP into CNT */
229  pcnt->CMD = PCNT_CMD_LCNTIM;
230 
231  /* Restore TOP? ('count' setting has been loaded into pcnt->TOP, better
232  * to use 'top' than pcnt->TOP in compare, since latter may in theory not
233  * be visible yet.) */
234  if (top != count)
235  {
236  /* Wait for command to sync LCNTIM before setting TOPB */
237  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
238 
239  /* Load into TOPB, we don't need to check for TOPB sync complete here,
240  * it has been ensured above. */
241  pcnt->TOPB = top;
242 
243  /* Load TOPB value into TOP */
244  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
245  pcnt->CMD = PCNT_CMD_LTOPBIM;
246  }
247 
248  /* Reenable if it was enabled */
249  if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
250  {
251  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD);
252  pcnt->CTRL = ctrl;
253  }
254 }
255 
256 
257 /***************************************************************************/
280 {
281  uint32_t tmp;
282 
283  EFM_ASSERT(PCNT_REF_VALID(pcnt));
284 
285  /* Set as specified */
286  tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK;
287  tmp |= (uint32_t)mode << _PCNT_CTRL_MODE_SHIFT;
288 
289  /* LF register about to be modified require sync. busy check */
290  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
291  pcnt->CTRL = tmp;
292 }
293 
294 #if defined(_PCNT_INPUT_MASK)
295 /***************************************************************************/
312  PCNT_PRSInput_TypeDef prsInput,
313  bool enable)
314 {
315  EFM_ASSERT(PCNT_REF_VALID(pcnt));
316 
317  /* Enable/disable the selected PRS input on the selected PCNT module. */
318  switch (prsInput)
319  {
320  /* Enable/disable PRS input S0. */
321  case pcntPRSInputS0:
323  break;
324 
325  /* Enable/disable PRS input S1. */
326  case pcntPRSInputS1:
328  break;
329 
330  /* Invalid parameter, asserted. */
331  default:
332  EFM_ASSERT(0);
333  break;
334  }
335 }
336 #endif
337 
338 
339 /***************************************************************************/
366 void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
367 {
368  EFM_ASSERT(PCNT_REF_VALID(pcnt));
369 
370  if (enable)
371  {
372  /* Wait for any ongoing LF synchronization to complete. This is just to
373  * protect against the rare case when a user:
374  * - modifies a register requiring LF sync
375  * - then enables freeze before LF sync completed
376  * - then modifies the same register again
377  * since modifying a register while it is in sync progress should be
378  * avoided. */
379  while (pcnt->SYNCBUSY)
380  ;
381 
383  }
384  else
385  {
386  pcnt->FREEZE = 0;
387  }
388 }
389 
390 
391 /***************************************************************************/
430 void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
431 {
432  unsigned int inst;
433  uint32_t tmp;
434 
435  EFM_ASSERT(PCNT_REF_VALID(pcnt));
436 
437 #ifdef PCNT0
438  if (PCNT0 == pcnt)
439  {
440  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->counter);
441  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->top);
442  }
443 #endif
444 
445 #ifdef PCNT1
446  if (PCNT1 == pcnt)
447  {
448  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->counter);
449  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->top);
450  }
451 #endif
452 
453 #ifdef PCNT2
454  if (PCNT2 == pcnt)
455  {
456  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->counter);
457  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->top);
458  }
459 #endif
460 
461  /* Map pointer to instance */
462  inst = PCNT_Map(pcnt);
463 
464 #if defined(_PCNT_INPUT_MASK)
465  /* Selecting the PRS channels for the PRS input sources of the PCNT. These are
466  * written with a Read-Modify-Write sequence in order to keep the value of the
467  * input enable bits which can be modified using PCNT_PRSInputEnable(). */
469  tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) |
470  ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT);
471  pcnt->INPUT = tmp;
472 #endif
473 
474  /* Build CTRL setting, except for mode */
475  tmp = 0;
476  if (init->negEdge)
477  {
478  tmp |= PCNT_CTRL_EDGE_NEG;
479  }
480 
481  if (init->countDown)
482  {
483  tmp |= PCNT_CTRL_CNTDIR_DOWN;
484  }
485 
486  if (init->filter)
487  {
488  tmp |= PCNT_CTRL_FILT;
489  }
490 
491 #if defined(PCNT_CTRL_HYST)
492  if (init->hyst)
493  {
494  tmp |= PCNT_CTRL_HYST;
495  }
496 #endif
497 
498 #if defined(PCNT_CTRL_S1CDIR)
499  if (init->s1CntDir)
500  {
501  tmp |= PCNT_CTRL_S1CDIR;
502  }
503 #endif
504 
505  /* Configure counter events for regular and auxiliary counter. */
506 #if defined(_PCNT_CTRL_CNTEV_SHIFT)
507  tmp |= init->cntEvent << _PCNT_CTRL_CNTEV_SHIFT;
508 #endif
509 
510 #if defined(_PCNT_CTRL_AUXCNTEV_SHIFT)
511  {
512  /* Modify the auxCntEvent value before writing to the AUXCNTEV field in
513  the CTRL register because the AUXCNTEV field values are different from
514  the CNTEV field values, and cntEvent and auxCntEvent are of the same type
515  PCNT_CntEvent_TypeDef.
516  */
517  uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */
518  switch (init->auxCntEvent)
519  {
520  case pcntCntEventBoth:
521  auxCntEventField = pcntCntEventNone;
522  break;
523  case pcntCntEventNone:
524  auxCntEventField = pcntCntEventBoth;
525  break;
526  case pcntCntEventUp:
527  case pcntCntEventDown:
528  auxCntEventField = init->auxCntEvent;
529  break;
530  default:
531  /* Invalid parameter, asserted. */
532  EFM_ASSERT(0);
533  break;
534  }
535  tmp |= auxCntEventField << _PCNT_CTRL_AUXCNTEV_SHIFT;
536  }
537 #endif
538 
539  /* Reset pulse counter while changing clock source. The reset bit */
540  /* is asynchronous, we don't have to check for SYNCBUSY. */
542 
543  /* Select LFACLK to clock in control setting */
544  CMU_PCNTClockExternalSet(inst, false);
545 
546  /* Handling depends on whether using external clock or not. */
547  switch (init->mode)
548  {
549  case pcntModeExtSingle:
550  case pcntModeExtQuad:
551  tmp |= init->mode << _PCNT_CTRL_MODE_SHIFT;
552 
553  /* In most cases, the SYNCBUSY bit is set due to reset bit set, and waiting
554  * for asynchronous reset bit is strictly not necessary.
555  * But in theory, other operations on CTRL register may have been done
556  * outside this function, so wait. */
557  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
558 
559  /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing
560  * the clock source to an external clock */
561  pcnt->CTRL = PCNT_CTRL_RSTEN;
562 
563  /* Wait until CTRL write synchronized into LF domain. */
564  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
565 
566  /* Change to external clock BEFORE disabling reset */
567  CMU_PCNTClockExternalSet(inst, true);
568 
569  /* Write to TOPB. If using external clock TOPB will sync to TOP at the same
570  * time as the mode. This will insure that if the user chooses to count
571  * down, the first "countable" pulse will make CNT go to TOP and not 0xFF
572  * (default TOP value). */
573  pcnt->TOPB = init->top;
574 
575  /* This bit has no effect on rev. C and onwards parts - for compatibility */
576  pcnt->CMD = PCNT_CMD_LTOPBIM;
577 
578  /* Write the CTRL register with the configurations.
579  * This should be written after TOPB in the eventuality of a pulse between
580  * these two writes that would cause the CTRL register to be synced one
581  * clock cycle earlier than the TOPB. */
582  pcnt->CTRL = tmp;
583 
584  /* There are no syncs for TOP, CMD or CTRL because the clock rate is unknown
585  * and the program could stall
586  * These will be synced within 3 clock cycles of the external clock /
587  * For the same reason CNT cannot be written here. */
588  break;
589 
590  /* pcntModeDisable */
591  /* pcntModeOvsSingle */
592  default:
593  /* No need to set disabled mode if already disabled. */
595  {
596  /* Set control to disabled mode, leave reset on until ensured disabled.
597  * We don't need to wait for CTRL SYNCBUSY completion here, it was
598  * triggered by reset bit above, which is asynchronous. */
600 
601  /* Wait until CTRL write synchronized into LF domain before proceeding
602  * to disable reset. */
603  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
604  }
605 
606  /* Disable reset bit, counter should now be in disabled mode. */
608 
609  /* Set counter and top values as specified. */
610  PCNT_CounterTopSet(pcnt, init->counter, init->top);
611 
612  /* Enter oversampling mode if selected. */
613  if (init->mode == pcntModeOvsSingle)
614  {
615  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
616  pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT);
617  }
618  break;
619  }
620 }
621 
622 
623 /***************************************************************************/
640 {
641  unsigned int inst;
642 
643  EFM_ASSERT(PCNT_REF_VALID(pcnt));
644 
645  /* Map pointer to instance and clock info */
646  inst = PCNT_Map(pcnt);
647 
648  pcnt->IEN = _PCNT_IEN_RESETVALUE;
649 
650  /* Notice that special SYNCBUSY handling is not applicable for the RSTEN
651  * bit of the control register, so we don't need to wait for it when only
652  * modifying RSTEN. The SYNCBUSY bit will be set, leading to a
653  * synchronization in the LF domain, with in reality no changes to LF domain.
654  * Enable reset of CNT and TOP register. */
656 
657  /* Select LFACLK as default */
658  CMU_PCNTClockExternalSet(inst, false);
659 
661 
662  /* Reset CTRL leaving RSTEN set */
664 
665  /* Disable reset after CTRL reg has been synchronized */
666  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
668 
669  /* Clear pending interrupts */
670  pcnt->IFC = _PCNT_IFC_MASK;
671 
672  /* Do not reset route register, setting should be done independently */
673 }
674 
675 #if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
676 /***************************************************************************/
693 void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) {
694  uint32_t ovscfg = 0;
695 
696  EFM_ASSERT(PCNT_REF_VALID(pcnt));
697 
698  /* Construct new filter setting value */
700  | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT);
701 
702  /* Set new configuration. LF register requires sync check before writing. */
703  PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG);
704  pcnt->OVSCFG = ovscfg;
705 
706 
707  /* Set new state of filter. LF register requires sync check before writing. */
708  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
709  if(enable)
710  {
711  pcnt->CTRL |= PCNT_CTRL_FILT;
712  }
713  else
714  {
715  pcnt->CTRL &= ~PCNT_CTRL_FILT;
716  }
717 }
718 #endif
719 
720 #if defined(PCNT_CTRL_TCCMODE_DEFAULT)
721 /***************************************************************************/
743  uint32_t ctrl = 0;
744  uint32_t mask = _PCNT_CTRL_TCCMODE_MASK
750 
751  EFM_ASSERT(PCNT_REF_VALID(pcnt));
752 
753  /* construct TCC part of configuration register */
754  ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT ) & _PCNT_CTRL_TCCMODE_MASK;
760 
761  /* Load new TCC config to PCNT. LF register requires sync check before write. */
762  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
763  pcnt->CTRL = (pcnt->CTRL & (~mask)) | ctrl;
764 }
765 #endif
766 
767 /***************************************************************************/
783 void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
784 {
785  EFM_ASSERT(PCNT_REF_VALID(pcnt));
786 
787  /* LF register about to be modified require sync. busy check */
788  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
789  pcnt->TOPB = val;
790 }
791 
792 
793 /***************************************************************************/
809 void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
810 {
811  EFM_ASSERT(PCNT_REF_VALID(pcnt));
812 
813 #ifdef PCNT0
814  if (PCNT0 == pcnt)
815  {
816  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > val);
817  }
818 #endif
819 
820 #ifdef PCNT1
821  if (PCNT1 == pcnt)
822  {
823  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > val);
824  }
825 #endif
826 
827 #ifdef PCNT2
828  if (PCNT2 == pcnt)
829  {
830  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > val);
831  }
832 #endif
833 
834  /* LF register about to be modified require sync. busy check */
835 
836  /* Load into TOPB */
837  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
838  pcnt->TOPB = val;
839 
840  /* Load TOPB value into TOP */
841  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
842  pcnt->CMD = PCNT_CMD_LTOPBIM;
843 }
844 
847 #endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */
Clock management unit (CMU) API.
void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
Set counter and top values.
Definition: em_pcnt.c:177
#define _PCNT_INPUT_S1PRSSEL_SHIFT
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
Definition: em_cmu.c:3685
PCNT_TCCPresc_Typedef prescaler
Definition: em_pcnt.h:340
#define PCNT_SYNCBUSY_CMD
void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode)
Set PCNT operational mode.
Definition: em_pcnt.c:279
Emlib peripheral API "assert" implementation.
#define PCNT_CTRL_RSTEN
#define PCNT_CTRL_S1CDIR
RAM and peripheral bit-field set and clear API.
__IO uint32_t TOPB
void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top value.
Definition: em_pcnt.c:809
void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, PCNT_PRSInput_TypeDef prsInput, bool enable)
Enable/disable the selected PRS input of PCNT.
Definition: em_pcnt.c:311
#define _PCNT_TOPB_RESETVALUE
#define _PCNT_CTRL_PRSGATEEN_SHIFT
#define _PCNT_CTRL_CNTEV_SHIFT
PCNT_TCCMode_TypeDef mode
Definition: em_pcnt.h:337
#define _PCNT_IEN_RESETVALUE
Pulse Counter (PCNT) peripheral API.
#define PCNT_SYNCBUSY_OVSCFG
#define PCNT_CTRL_EDGE_NEG
#define _PCNT_OVSCFG_FILTLEN_MASK
#define PCNT_CTRL_FILT
__IO uint32_t IEN
#define _PCNT_CTRL_RESETVALUE
PCNT_CntEvent_TypeDef cntEvent
Definition: em_pcnt.h:221
#define _PCNT_CTRL_TCCPRSPOL_MASK
#define _PCNT_INPUT_S1PRSEN_SHIFT
PCNT_PRSInput_TypeDef
Definition: em_pcnt.h:165
#define _PCNT_OVSCFG_FLUTTERRM_SHIFT
uint32_t counter
Definition: em_pcnt.h:187
#define _PCNT_INPUT_S0PRSSEL_SHIFT
#define _PCNT_CTRL_TCCPRSSEL_SHIFT
#define PCNT_CMD_LCNTIM
#define _PCNT_INPUT_S0PRSSEL_MASK
PCNT_CntEvent_TypeDef auxCntEvent
Definition: em_pcnt.h:225
__IO uint32_t CTRL
#define PCNT_SYNCBUSY_TOPB
uint32_t top
Definition: em_pcnt.h:193
__IO uint32_t OVSCFG
__IO uint32_t FREEZE
__IO uint32_t IFC
PCNT_Mode_TypeDef
Definition: em_pcnt.h:81
void PCNT_CounterReset(PCNT_TypeDef *pcnt)
Reset PCNT counters and TOP register.
Definition: em_pcnt.c:141
__I uint32_t SYNCBUSY
void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
Init pulse counter.
Definition: em_pcnt.c:430
PCNT_PRSSel_TypeDef s1PRS
Definition: em_pcnt.h:231
#define _PCNT_INPUT_S1PRSSEL_MASK
#define _PCNT_CTRL_PRSGATEEN_MASK
#define PCNT_CTRL_MODE_DISABLE
PCNT_PRSSel_TypeDef s0PRS
Definition: em_pcnt.h:228
PCNT_PRSSel_TypeDef tccPRS
Definition: em_pcnt.h:346
void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable)
Set filter configuration.
Definition: em_pcnt.c:693
#define PCNT0_CNT_SIZE
Definition: em_pcnt.h:62
void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top buffer value.
Definition: em_pcnt.c:783
#define _PCNT_CTRL_MODE_MASK
#define PCNT_CTRL_CNTDIR_DOWN
#define _PCNT_CTRL_TCCMODE_SHIFT
#define _PCNT_CTRL_TCCPRESC_SHIFT
#define _PCNT_OVSCFG_FILTLEN_SHIFT
#define PCNT_FREEZE_REGFREEZE
__IO uint32_t INPUT
#define PCNT0
#define _PCNT_CTRL_MODE_SHIFT
void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
PCNT register synchronization freeze control.
Definition: em_pcnt.c:366
#define _PCNT_CTRL_TCCPRESC_MASK
#define _PCNT_CTRL_TCCMODE_MASK
#define _PCNT_CTRL_TCCPRSPOL_SHIFT
#define PCNT_CMD_LTOPBIM
#define _PCNT_CTRL_RSTEN_SHIFT
#define _PCNT_IFC_MASK
#define _PCNT_CTRL_TCCPRSSEL_MASK
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146
#define _PCNT_CTRL_TCCCOMP_MASK
#define _PCNT_CTRL_AUXCNTEV_SHIFT
__IO uint32_t CMD
#define PCNT0_BASE
bool prsGateEnable
Definition: em_pcnt.h:355
#define _PCNT_INPUT_S0PRSEN_SHIFT
void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config)
Set Triggered Compare and Clear configuration.
Definition: em_pcnt.c:742
PCNT_TCCComp_Typedef compare
Definition: em_pcnt.h:343
PCNT_Mode_TypeDef mode
Definition: em_pcnt.h:181
#define PCNT_SYNCBUSY_CTRL
void PCNT_Reset(PCNT_TypeDef *pcnt)
Reset PCNT to same state as after a HW reset.
Definition: em_pcnt.c:639
#define _PCNT_CTRL_TCCCOMP_SHIFT
#define PCNT_CTRL_HYST
bool prsPolarity
Definition: em_pcnt.h:351