34 #ifndef SILICON_LABS_EFM32PG1B200F256GM48_H
35 #define SILICON_LABS_EFM32PG1B200F256GM48_H
98 #define __MPU_PRESENT 1
99 #define __FPU_PRESENT 1
100 #define __NVIC_PRIO_BITS 3
101 #define __Vendor_SysTickConfig 0
111 #define _EFM32_PEARL_FAMILY 1
113 #define _SILICON_LABS_32B_PLATFORM_2
114 #define _SILICON_LABS_32B_PLATFORM 2
117 #if !defined(EFM32PG1B200F256GM48)
118 #define EFM32PG1B200F256GM48 1
122 #define PART_NUMBER "EFM32PG1B200F256GM48"
125 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL)
126 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
127 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL)
128 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
129 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
130 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL)
131 #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL)
132 #define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL)
133 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL)
134 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL)
135 #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL)
136 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL)
137 #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL)
138 #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL)
139 #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL)
140 #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL)
141 #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL)
142 #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL)
143 #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL)
144 #define CRYPTO_MEM_BITS ((uint32_t) 0x10UL)
145 #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL)
146 #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL)
147 #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL)
148 #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL)
149 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL)
150 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL)
151 #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL)
152 #define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL)
153 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
154 #define PER_MEM_SIZE ((uint32_t) 0xE8000UL)
155 #define PER_MEM_END ((uint32_t) 0x400E7FFFUL)
156 #define PER_MEM_BITS ((uint32_t) 0x20UL)
157 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
158 #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL)
159 #define RAM_MEM_END ((uint32_t) 0x20007BFFUL)
160 #define RAM_MEM_BITS ((uint32_t) 0x15UL)
163 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
164 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
167 #define FLASH_BASE (0x00000000UL)
168 #define FLASH_SIZE (0x00040000UL)
169 #define FLASH_PAGE_SIZE 2048
170 #define SRAM_BASE (0x20000000UL)
171 #define SRAM_SIZE (0x00008000UL)
172 #define __CM4_REV 0x001
173 #define PRS_CHAN_COUNT 12
174 #define DMA_CHAN_COUNT 8
177 #define AFCHAN_MAX 72
178 #define AFCHANLOC_MAX 32
180 #define AFACHAN_MAX 61
184 #define TIMER_PRESENT
185 #define TIMER_COUNT 2
186 #define USART_PRESENT
187 #define USART_COUNT 2
188 #define LEUART_PRESENT
189 #define LEUART_COUNT 1
190 #define LETIMER_PRESENT
191 #define LETIMER_COUNT 1
212 #define CRYPTO_PRESENT
213 #define CRYPTO_COUNT 1
220 #define FPUEH_PRESENT
221 #define FPUEH_COUNT 1
222 #define GPCRC_PRESENT
223 #define GPCRC_COUNT 1
224 #define CRYOTIMER_PRESENT
225 #define CRYOTIMER_COUNT 1
228 #define BOOTLOADER_PRESENT
229 #define BOOTLOADER_COUNT 1
231 #include "core_cm4.h"
282 #define MSC_BASE (0x400E0000UL)
283 #define EMU_BASE (0x400E3000UL)
284 #define RMU_BASE (0x400E5000UL)
285 #define CMU_BASE (0x400E4000UL)
286 #define CRYPTO_BASE (0x400F0000UL)
287 #define GPIO_BASE (0x4000A000UL)
288 #define PRS_BASE (0x400E6000UL)
289 #define LDMA_BASE (0x400E2000UL)
290 #define FPUEH_BASE (0x400E1000UL)
291 #define GPCRC_BASE (0x4001C000UL)
292 #define TIMER0_BASE (0x40018000UL)
293 #define TIMER1_BASE (0x40018400UL)
294 #define USART0_BASE (0x40010000UL)
295 #define USART1_BASE (0x40010400UL)
296 #define LEUART0_BASE (0x4004A000UL)
297 #define LETIMER0_BASE (0x40046000UL)
298 #define CRYOTIMER_BASE (0x4001E000UL)
299 #define PCNT0_BASE (0x4004E000UL)
300 #define I2C0_BASE (0x4000C000UL)
301 #define ADC0_BASE (0x40002000UL)
302 #define ACMP0_BASE (0x40000000UL)
303 #define ACMP1_BASE (0x40000400UL)
304 #define IDAC0_BASE (0x40006000UL)
305 #define RTCC_BASE (0x40042000UL)
306 #define WDOG0_BASE (0x40052000UL)
307 #define DEVINFO_BASE (0x0FE081B0UL)
308 #define ROMTABLE_BASE (0xE00FFFD0UL)
309 #define LOCKBITS_BASE (0x0FE04000UL)
310 #define USERDATA_BASE (0x0FE00000UL)
319 #define MSC ((MSC_TypeDef *) MSC_BASE)
320 #define EMU ((EMU_TypeDef *) EMU_BASE)
321 #define RMU ((RMU_TypeDef *) RMU_BASE)
322 #define CMU ((CMU_TypeDef *) CMU_BASE)
323 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE)
324 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
325 #define PRS ((PRS_TypeDef *) PRS_BASE)
326 #define LDMA ((LDMA_TypeDef *) LDMA_BASE)
327 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE)
328 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE)
329 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
330 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
331 #define USART0 ((USART_TypeDef *) USART0_BASE)
332 #define USART1 ((USART_TypeDef *) USART1_BASE)
333 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
334 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
335 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE)
336 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
337 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
338 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
339 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
340 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
341 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)
342 #define RTCC ((RTCC_TypeDef *) RTCC_BASE)
343 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE)
344 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
345 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
354 #define TIMER_OFFSET 0x400
355 #define USART_OFFSET 0x400
356 #define LEUART_OFFSET 0x400
357 #define LETIMER_OFFSET 0x400
358 #define PCNT_OFFSET 0x400
359 #define I2C_OFFSET 0x400
360 #define ADC_OFFSET 0x400
361 #define ACMP_OFFSET 0x400
362 #define IDAC_OFFSET 0x400
363 #define WDOG_OFFSET 0x400
373 #include "efm32pg1b_prs_signals.h"
380 #define MSC_UNLOCK_CODE 0x1B71
381 #define EMU_UNLOCK_CODE 0xADE8
382 #define RMU_UNLOCK_CODE 0xE084
383 #define CMU_UNLOCK_CODE 0x580E
384 #define GPIO_UNLOCK_CODE 0xA534
385 #define TIMER_UNLOCK_CODE 0xCE80
386 #define RTCC_UNLOCK_CODE 0xAEE8
397 #include "efm32pg1b_af_ports.h"
415 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
416 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
EFM32PG1B_TIMER_CC register and bit field definitions.
EFM32PG1B_CRYOTIMER register and bit field definitions.
EFM32PG1B_LEUART register and bit field definitions.
EFM32PG1B_EMU register and bit field definitions.
EFM32PG1B_TIMER register and bit field definitions.
EFM32PG1B_ROMTABLE register and bit field definitions.
EFM32PG1B_DEVINFO register and bit field definitions.
EFM32PG1B_LETIMER register and bit field definitions.
EFM32PG1B_GPIO register and bit field definitions.
EFM32PG1B_WDOG_PCH register and bit field definitions.
EFM32PG1B_IDAC register and bit field definitions.
EFM32PG1B_LDMA_CH register and bit field definitions.
EFM32PG1B_PRS_CH register and bit field definitions.
EFM32PG1B_AF_PINS register and bit field definitions.
EFM32PG1B_FPUEH register and bit field definitions.
EFM32PG1B_CMU register and bit field definitions.
EFM32PG1B_I2C register and bit field definitions.
EFM32PG1B_RTCC register and bit field definitions.
EFM32PG1B_USART register and bit field definitions.
EFM32PG1B_RMU register and bit field definitions.
EFM32PG1B_GPIO_P register and bit field definitions.
EFM32PG1B_MSC register and bit field definitions.
CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
EFM32PG1B_WDOG register and bit field definitions.
EFM32PG1B_RTCC_CC register and bit field definitions.
EFM32PG1B_ADC register and bit field definitions.
EFM32PG1B_PRS register and bit field definitions.
EFM32PG1B_GPCRC register and bit field definitions.
EFM32PG1B_RTCC_RET register and bit field definitions.
EFM32PG1B_LDMA register and bit field definitions.
EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions.
EFM32PG1B_CRYPTO register and bit field definitions.
EFM32PG1B_PCNT register and bit field definitions.
EFM32PG1B_ACMP register and bit field definitions.
EFM32PG1B_DMAREQ register and bit field definitions.