34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
60 void EBI_Init(
const EBI_Init_TypeDef *ebiInit)
62 uint32_t ctrl = EBI->CTRL;
64 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
69 EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
71 EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
73 EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
75 EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
77 EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
79 EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
82 EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
84 EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
86 EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
88 EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
90 EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
94 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
95 if (ebiInit->banks & EBI_BANK0)
97 ctrl &= ~(_EBI_CTRL_MODE_MASK
98 | _EBI_CTRL_ARDYEN_MASK
99 | _EBI_CTRL_ARDYTODIS_MASK
101 | _EBI_CTRL_NOIDLE_MASK
102 | _EBI_CTRL_BANK0EN_MASK);
103 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
104 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
105 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
106 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
107 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
108 if ( ebiInit->enable)
110 ctrl |= EBI_CTRL_BANK0EN;
113 if (ebiInit->banks & EBI_BANK1)
115 ctrl &= ~(_EBI_CTRL_BL1_MASK
116 | _EBI_CTRL_MODE1_MASK
117 | _EBI_CTRL_ARDY1EN_MASK
118 | _EBI_CTRL_ARDYTO1DIS_MASK
119 | _EBI_CTRL_NOIDLE1_MASK
120 | _EBI_CTRL_BANK1EN_MASK);
121 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
122 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
123 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
124 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
125 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
126 if ( ebiInit->enable)
128 ctrl |= EBI_CTRL_BANK1EN;
131 if (ebiInit->banks & EBI_BANK2)
133 ctrl &= ~(_EBI_CTRL_BL2_MASK
134 | _EBI_CTRL_MODE2_MASK
135 | _EBI_CTRL_ARDY2EN_MASK
136 | _EBI_CTRL_ARDYTO2DIS_MASK
137 | _EBI_CTRL_NOIDLE2_MASK
138 | _EBI_CTRL_BANK2EN_MASK);
139 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
140 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
141 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
142 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
143 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
144 if ( ebiInit->enable)
146 ctrl |= EBI_CTRL_BANK2EN;
149 if (ebiInit->banks & EBI_BANK3)
151 ctrl &= ~(_EBI_CTRL_BL3_MASK
152 | _EBI_CTRL_MODE3_MASK
153 | _EBI_CTRL_ARDY3EN_MASK
154 | _EBI_CTRL_ARDYTO3DIS_MASK
155 | _EBI_CTRL_NOIDLE3_MASK
156 | _EBI_CTRL_BANK3EN_MASK);
157 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
158 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
159 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
160 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
161 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
162 if ( ebiInit->enable)
164 ctrl |= EBI_CTRL_BANK3EN;
168 ctrl &= ~(_EBI_CTRL_MODE_MASK
169 | _EBI_CTRL_ARDYEN_MASK
170 | _EBI_CTRL_ARDYTODIS_MASK
171 | _EBI_CTRL_BANK0EN_MASK
172 | _EBI_CTRL_BANK1EN_MASK
173 | _EBI_CTRL_BANK2EN_MASK
174 | _EBI_CTRL_BANK3EN_MASK);
175 if ( ebiInit->enable)
177 if ( ebiInit->banks & EBI_BANK0 )
179 ctrl |= EBI_CTRL_BANK0EN;
181 if ( ebiInit->banks & EBI_BANK1 )
183 ctrl |= EBI_CTRL_BANK1EN;
185 if ( ebiInit->banks & EBI_BANK2 )
187 ctrl |= EBI_CTRL_BANK2EN;
189 if ( ebiInit->banks & EBI_BANK3 )
191 ctrl |= EBI_CTRL_BANK3EN;
194 ctrl |= ebiInit->mode;
195 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
196 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
200 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
201 EBI_BankReadTimingSet(ebiInit->banks,
202 ebiInit->readSetupCycles,
203 ebiInit->readStrobeCycles,
204 ebiInit->readHoldCycles);
205 EBI_BankReadTimingConfig(ebiInit->banks,
206 ebiInit->readPageMode,
207 ebiInit->readPrefetch,
208 ebiInit->readHalfRE);
209 EBI_BankWriteTimingSet(ebiInit->banks,
210 ebiInit->writeSetupCycles,
211 ebiInit->writeStrobeCycles,
212 ebiInit->writeHoldCycles);
213 EBI_BankWriteTimingConfig(ebiInit->banks,
214 ebiInit->writeBufferDisable,
215 ebiInit->writeHalfWE);
216 EBI_BankAddressTimingSet(ebiInit->banks,
217 ebiInit->addrSetupCycles,
218 ebiInit->addrHoldCycles);
219 EBI_BankAddressTimingConfig(ebiInit->banks,
220 ebiInit->addrHalfALE);
222 EBI_ReadTimingSet(ebiInit->readSetupCycles,
223 ebiInit->readStrobeCycles,
224 ebiInit->readHoldCycles);
225 EBI_WriteTimingSet(ebiInit->writeSetupCycles,
226 ebiInit->writeStrobeCycles,
227 ebiInit->writeHoldCycles);
228 EBI_AddressTimingSet(ebiInit->addrSetupCycles,
229 ebiInit->addrHoldCycles);
236 switch (ebiInit->mode)
238 case ebiModeD16A16ALE:
239 case ebiModeD8A24ALE:
243 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
251 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
253 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
254 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
256 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
259 if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
261 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
268 EBI_ChipSelectEnable(ebiInit->csLines,
true);
276 void EBI_Disable(
void)
279 EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
281 EBI->CTRL = _EBI_CTRL_RESETVALUE;
295 void EBI_BankEnable(uint32_t banks,
bool enable)
297 if (banks & EBI_BANK0)
301 if (banks & EBI_BANK1)
305 if (banks & EBI_BANK2)
309 if (banks & EBI_BANK3)
326 uint32_t EBI_BankAddress(uint32_t bank)
328 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
329 if(EBI->CTRL & EBI_CTRL_ALTMAP)
334 return(EBI_MEM_BASE);
337 return(EBI_MEM_BASE + 0x10000000UL);
340 return(EBI_MEM_BASE + 0x20000000UL);
343 return(EBI_MEM_BASE + 0x30000000UL);
354 return(EBI_MEM_BASE);
357 return(EBI_MEM_BASE + 0x04000000UL);
360 return(EBI_MEM_BASE + 0x08000000UL);
363 return(EBI_MEM_BASE + 0x0C000000UL);
383 void EBI_ChipSelectEnable(uint32_t cs,
bool enable)
414 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
419 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
422 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
425 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
428 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
431 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
433 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
435 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
437 case ebiLineTFTVSync:
438 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
440 case ebiLineTFTHSync:
441 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
443 case ebiLineTFTDataEn:
444 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
447 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
450 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
474 void EBI_ReadTimingSet(
int setupCycles,
int strobeCycles,
int holdCycles)
479 EFM_ASSERT(setupCycles < 4);
480 EFM_ASSERT(strobeCycles < 16);
481 EFM_ASSERT(holdCycles < 4);
484 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
485 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
486 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
489 EBI->RDTIMING = (EBI->RDTIMING
490 & ~(_EBI_RDTIMING_RDSETUP_MASK
491 | _EBI_RDTIMING_RDSTRB_MASK
492 | _EBI_RDTIMING_RDHOLD_MASK))
510 void EBI_WriteTimingSet(
int setupCycles,
int strobeCycles,
int holdCycles)
512 uint32_t writeTiming;
515 EFM_ASSERT(setupCycles < 4);
516 EFM_ASSERT(strobeCycles < 16);
517 EFM_ASSERT(holdCycles < 4);
520 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
521 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
522 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
524 EBI->WRTIMING = (EBI->WRTIMING
525 & ~(_EBI_WRTIMING_WRSETUP_MASK
526 | _EBI_WRTIMING_WRSTRB_MASK
527 | _EBI_WRTIMING_WRHOLD_MASK))
543 void EBI_AddressTimingSet(
int setupCycles,
int holdCycles)
545 uint32_t addressLatchTiming;
548 EFM_ASSERT(setupCycles < 4);
549 EFM_ASSERT(holdCycles < 4);
552 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
553 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
555 EBI->ADDRTIMING = (EBI->ADDRTIMING
556 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
557 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
558 | addressLatchTiming;
561 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
569 void EBI_TFTInit(
const EBI_TFTInit_TypeDef *ebiTFTInit)
574 EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
577 EBI_TFTSizeSet(ebiTFTInit->hsize,
579 EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
580 ebiTFTInit->hPorchBack,
581 ebiTFTInit->hPulseWidth);
582 EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
583 ebiTFTInit->vPorchBack,
584 ebiTFTInit->vPulseWidth);
587 EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
588 ebiTFTInit->startPosition,
589 ebiTFTInit->setupCycles,
590 ebiTFTInit->holdCycles);
593 EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
594 EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
595 EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
596 EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
597 EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
600 ctrl = (uint32_t)ebiTFTInit->bank
601 | (uint32_t)ebiTFTInit->width
602 | (uint32_t)ebiTFTInit->colSrc
603 | (uint32_t)ebiTFTInit->interleave
604 | (uint32_t)ebiTFTInit->fbTrigger
605 | (uint32_t)(ebiTFTInit->shiftDClk ==
true
606 ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
607 | (uint32_t)ebiTFTInit->maskBlend
608 | (uint32_t)ebiTFTInit->driveMode;
613 if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
615 EBI->ROUTE |= EBI_ROUTE_TFTPEN;
629 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
631 EFM_ASSERT((horizontal-1) < 1024);
632 EFM_ASSERT((vertical-1) < 1024);
634 EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
635 | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
649 void EBI_TFTHPorchSet(
int front,
int back,
int pulseWidth)
651 EFM_ASSERT(front < 256);
652 EFM_ASSERT(back < 256);
653 EFM_ASSERT((pulseWidth-1) < 128);
655 EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
656 | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
657 | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
672 void EBI_TFTVPorchSet(
int front,
int back,
int pulseWidth)
674 EFM_ASSERT(front < 256);
675 EFM_ASSERT(back < 256);
676 EFM_ASSERT((pulseWidth-1) < 128);
678 EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
679 | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
680 | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
700 void EBI_TFTTimingSet(
int dclkPeriod,
int start,
int setup,
int hold)
702 EFM_ASSERT(dclkPeriod < 2048);
703 EFM_ASSERT(start < 2048);
704 EFM_ASSERT(setup < 4);
705 EFM_ASSERT(hold < 4);
707 EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
708 | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
709 | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
710 | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
714 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
731 void EBI_BankReadTimingConfig(uint32_t banks,
bool pageMode,
bool prefetch,
bool halfRE)
734 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
737 if( banks & EBI_BANK0 )
739 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
740 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
743 if( banks & EBI_BANK1 )
745 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
746 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
749 if( banks & EBI_BANK2 )
751 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
752 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
755 if( banks & EBI_BANK3 )
757 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
758 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
780 void EBI_BankReadTimingSet(uint32_t banks,
int setupCycles,
int strobeCycles,
int holdCycles)
785 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
788 EFM_ASSERT(setupCycles < 4);
789 EFM_ASSERT(strobeCycles < 64);
790 EFM_ASSERT(holdCycles < 4);
793 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
794 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
795 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
797 if (banks & EBI_BANK0)
799 EBI->RDTIMING = (EBI->RDTIMING
800 & ~(_EBI_RDTIMING_RDSETUP_MASK
801 | _EBI_RDTIMING_RDSTRB_MASK
802 | _EBI_RDTIMING_RDHOLD_MASK))
805 if (banks & EBI_BANK1)
807 EBI->RDTIMING1 = (EBI->RDTIMING1
808 & ~(_EBI_RDTIMING1_RDSETUP_MASK
809 | _EBI_RDTIMING1_RDSTRB_MASK
810 | _EBI_RDTIMING1_RDHOLD_MASK))
813 if (banks & EBI_BANK2)
815 EBI->RDTIMING2 = (EBI->RDTIMING2
816 & ~(_EBI_RDTIMING2_RDSETUP_MASK
817 | _EBI_RDTIMING2_RDSTRB_MASK
818 | _EBI_RDTIMING2_RDHOLD_MASK))
821 if (banks & EBI_BANK3)
823 EBI->RDTIMING3 = (EBI->RDTIMING3
824 & ~(_EBI_RDTIMING3_RDSETUP_MASK
825 | _EBI_RDTIMING3_RDSTRB_MASK
826 | _EBI_RDTIMING3_RDHOLD_MASK))
845 void EBI_BankWriteTimingConfig(uint32_t banks,
bool writeBufDisable,
bool halfWE)
848 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
851 if( banks & EBI_BANK0 )
853 BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
856 if( banks & EBI_BANK1 )
858 BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
861 if( banks & EBI_BANK2 )
863 BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
866 if( banks & EBI_BANK3 )
868 BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
890 void EBI_BankWriteTimingSet(uint32_t banks,
int setupCycles,
int strobeCycles,
int holdCycles)
892 uint32_t writeTiming;
895 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
898 EFM_ASSERT(setupCycles < 4);
899 EFM_ASSERT(strobeCycles < 64);
900 EFM_ASSERT(holdCycles < 4);
903 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
904 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
905 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
907 if (banks & EBI_BANK0)
909 EBI->WRTIMING = (EBI->WRTIMING
910 & ~(_EBI_WRTIMING_WRSETUP_MASK
911 | _EBI_WRTIMING_WRSTRB_MASK
912 | _EBI_WRTIMING_WRHOLD_MASK))
915 if (banks & EBI_BANK1)
917 EBI->WRTIMING1 = (EBI->WRTIMING1
918 & ~(_EBI_WRTIMING1_WRSETUP_MASK
919 | _EBI_WRTIMING1_WRSTRB_MASK
920 | _EBI_WRTIMING1_WRHOLD_MASK))
923 if (banks & EBI_BANK2)
925 EBI->WRTIMING2 = (EBI->WRTIMING2
926 & ~(_EBI_WRTIMING2_WRSETUP_MASK
927 | _EBI_WRTIMING2_WRSTRB_MASK
928 | _EBI_WRTIMING2_WRHOLD_MASK))
931 if (banks & EBI_BANK3)
933 EBI->WRTIMING3 = (EBI->WRTIMING3
934 & ~(_EBI_WRTIMING3_WRSETUP_MASK
935 | _EBI_WRTIMING3_WRSTRB_MASK
936 | _EBI_WRTIMING3_WRHOLD_MASK))
952 void EBI_BankAddressTimingConfig(uint32_t banks,
bool halfALE)
955 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
957 if( banks & EBI_BANK0 )
959 BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
961 if( banks & EBI_BANK1 )
963 BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
965 if( banks & EBI_BANK2 )
967 BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
969 if( banks & EBI_BANK3 )
971 BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
990 void EBI_BankAddressTimingSet(uint32_t banks,
int setupCycles,
int holdCycles)
992 uint32_t addressLatchTiming;
995 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
998 EFM_ASSERT(setupCycles < 4);
999 EFM_ASSERT(holdCycles < 4);
1002 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
1003 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
1005 if (banks & EBI_BANK0)
1007 EBI->ADDRTIMING = (EBI->ADDRTIMING
1008 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
1009 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
1010 | addressLatchTiming;
1012 if (banks & EBI_BANK1)
1014 EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
1015 & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
1016 | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
1017 | addressLatchTiming;
1019 if (banks & EBI_BANK2)
1021 EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
1022 & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
1023 | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
1024 | addressLatchTiming;
1026 if (banks & EBI_BANK3)
1028 EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
1029 & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
1030 | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
1031 | addressLatchTiming;
1050 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
1052 uint32_t bankSet = 0;
1053 volatile uint32_t *polRegister = 0;
1056 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1060 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1061 if (banks & EBI_BANK0)
1063 polRegister = &EBI->POLARITY;
1064 bankSet = EBI_BANK0;
1066 if (banks & EBI_BANK1)
1068 polRegister = &EBI->POLARITY1;
1069 bankSet = EBI_BANK1;
1071 if (banks & EBI_BANK2)
1073 polRegister = &EBI->POLARITY2;
1074 bankSet = EBI_BANK2;
1076 if (banks & EBI_BANK3)
1078 polRegister = &EBI->POLARITY3;
1079 bankSet = EBI_BANK3;
1082 polRegister = &EBI->POLARITY;
1104 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1108 case ebiLineTFTVSync:
1109 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
1111 case ebiLineTFTHSync:
1112 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
1114 case ebiLineTFTDataEn:
1115 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
1117 case ebiLineTFTDClk:
1118 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
1121 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
1128 banks = banks & ~bankSet;
1144 void EBI_BankByteLaneEnable(uint32_t banks,
bool enable)
1147 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1150 if (banks & EBI_BANK0)
1154 if (banks & EBI_BANK1)
1158 if (banks & EBI_BANK2)
1162 if (banks & EBI_BANK3)
1177 void EBI_AltMapEnable(
bool enable)
Emlib peripheral API "assert" implementation.
RAM and peripheral bit-field set and clear API.
External Bus Iterface (EBI) peripheral API.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.