EZR32 Leopard Gecko Software Documentation  ezr32lg-doc-4.2.1
ezr32lg330f256r69.h
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1 /**************************************************************************/
34 #ifndef EZR32LG330F256R69_H
35 #define EZR32LG330F256R69_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /**************************************************************************/
46 /**************************************************************************/
52 typedef enum IRQn
53 {
54 /****** Cortex-M3 Processor Exceptions Numbers *******************************************/
58  BusFault_IRQn = -11,
60  SVCall_IRQn = -5,
62  PendSV_IRQn = -2,
63  SysTick_IRQn = -1,
65 /****** EZR32LG Peripheral Interrupt Numbers *********************************************/
66 
67  DMA_IRQn = 0,
72  USB_IRQn = 5,
73  ACMP0_IRQn = 6,
74  ADC0_IRQn = 7,
75  DAC0_IRQn = 8,
76  I2C0_IRQn = 9,
77  I2C1_IRQn = 10,
79  TIMER1_IRQn = 12,
80  TIMER2_IRQn = 13,
81  TIMER3_IRQn = 14,
84  LESENSE_IRQn = 17,
91  LEUART0_IRQn = 24,
92  LEUART1_IRQn = 25,
94  PCNT0_IRQn = 27,
95  PCNT1_IRQn = 28,
96  PCNT2_IRQn = 29,
97  RTC_IRQn = 30,
98  BURTC_IRQn = 31,
99  CMU_IRQn = 32,
100  VCMP_IRQn = 33,
101  MSC_IRQn = 35,
102  AES_IRQn = 36,
103  EMU_IRQn = 38,
104 } IRQn_Type;
105 
106 /**************************************************************************/
111 #define __MPU_PRESENT 1
112 #define __NVIC_PRIO_BITS 3
113 #define __Vendor_SysTickConfig 0
117 /**************************************************************************/
123 #define _EFM32_GIANT_FAMILY 1
124 #define _EFM_DEVICE
125 #define _EZR32_LEOPARD_FAMILY 1
126 #define _EZR_DEVICE
127 #define _SILICON_LABS_32B_PLATFORM_1
128 #define _SILICON_LABS_32B_PLATFORM 1
130 /* If part number is not defined as compiler option, define it */
131 #if !defined(EZR32LG330F256R69)
132 #define EZR32LG330F256R69 1
133 #endif
134 
136 #define PART_NUMBER "EZR32LG330F256R69"
139 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
140 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
141 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
142 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
143 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
144 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
145 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
146 #define AES_MEM_BITS ((uint32_t) 0x10UL)
147 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL)
148 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL)
149 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL)
150 #define USBC_MEM_BITS ((uint32_t) 0x18UL)
151 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
152 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
153 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
154 #define PER_MEM_BITS ((uint32_t) 0x20UL)
155 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
156 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
157 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
158 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
159 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
160 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
161 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
162 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
165 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
166 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
169 #define FLASH_BASE (0x00000000UL)
170 #define FLASH_SIZE (0x00040000UL)
171 #define FLASH_PAGE_SIZE 2048
172 #define SRAM_BASE (0x20000000UL)
173 #define SRAM_SIZE (0x00008000UL)
174 #define __CM3_REV 0x201
175 #define PRS_CHAN_COUNT 12
176 #define DMA_CHAN_COUNT 12
179 #define AFCHAN_MAX 84
180 #define AFCHANLOC_MAX 7
181 
182 #define AFACHAN_MAX 48
183 
184 /* Part number capabilities */
185 
186 #define USARTRF_PRESENT
187 #define USARTRF_COUNT 1
188 #define USART_PRESENT
189 #define USART_COUNT 2
190 #define UART_PRESENT
191 #define UART_COUNT 2
192 #define TIMER_PRESENT
193 #define TIMER_COUNT 4
194 #define ACMP_PRESENT
195 #define ACMP_COUNT 2
196 #define LEUART_PRESENT
197 #define LEUART_COUNT 2
198 #define LETIMER_PRESENT
199 #define LETIMER_COUNT 1
200 #define PCNT_PRESENT
201 #define PCNT_COUNT 3
202 #define I2C_PRESENT
203 #define I2C_COUNT 2
204 #define ADC_PRESENT
205 #define ADC_COUNT 1
206 #define DAC_PRESENT
207 #define DAC_COUNT 1
208 #define DMA_PRESENT
209 #define DMA_COUNT 1
210 #define AES_PRESENT
211 #define AES_COUNT 1
212 #define USBC_PRESENT
213 #define USBC_COUNT 1
214 #define USB_PRESENT
215 #define USB_COUNT 1
216 #define LE_PRESENT
217 #define LE_COUNT 1
218 #define MSC_PRESENT
219 #define MSC_COUNT 1
220 #define EMU_PRESENT
221 #define EMU_COUNT 1
222 #define RMU_PRESENT
223 #define RMU_COUNT 1
224 #define CMU_PRESENT
225 #define CMU_COUNT 1
226 #define LESENSE_PRESENT
227 #define LESENSE_COUNT 1
228 #define RTC_PRESENT
229 #define RTC_COUNT 1
230 #define GPIO_PRESENT
231 #define GPIO_COUNT 1
232 #define VCMP_PRESENT
233 #define VCMP_COUNT 1
234 #define PRS_PRESENT
235 #define PRS_COUNT 1
236 #define BU_PRESENT
237 #define BU_COUNT 1
238 #define BURTC_PRESENT
239 #define BURTC_COUNT 1
240 #define HFXTAL_PRESENT
241 #define HFXTAL_COUNT 1
242 #define LFXTAL_PRESENT
243 #define LFXTAL_COUNT 1
244 #define WDOG_PRESENT
245 #define WDOG_COUNT 1
246 #define DBG_PRESENT
247 #define DBG_COUNT 1
248 #define ETM_PRESENT
249 #define ETM_COUNT 1
250 #define BOOTLOADER_PRESENT
251 #define BOOTLOADER_COUNT 1
252 #define ANALOG_PRESENT
253 #define ANALOG_COUNT 1
254 #define RF_PRESENT
255 #define RF_COUNT 1
256 
257 /**************************************************************************/
262 #define RF_USARTRF_LOCATION 0
263 #define RF_USARTRF_CS_PORT 4
264 #define RF_USARTRF_CS_PIN 9
265 #define RF_USARTRF_CLK_PORT 4
266 #define RF_USARTRF_CLK_PIN 12
267 #define RF_USARTRF_MISO_PORT 4
268 #define RF_USARTRF_MISO_PIN 11
269 #define RF_USARTRF_MOSI_PORT 4
270 #define RF_USARTRF_MOSI_PIN 10
271 #define RF_INT_PORT 4
272 #define RF_INT_PIN 13
273 #define RF_GPIO0_PORT 0
274 #define RF_GPIO0_PIN 15
275 #define RF_GPIO1_PORT 4
276 #define RF_GPIO1_PIN 14
277 #define RF_SDN_PORT 4
278 #define RF_SDN_PIN 8
282 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
283 #include "system_ezr32lg.h" /* System Header */
284 
287 /**************************************************************************/
293 #include "ezr32lg_dma_ch.h"
294 #include "ezr32lg_dma.h"
295 #include "ezr32lg_aes.h"
296 #include "ezr32lg_usb_hc.h"
297 #include "ezr32lg_usb_diep.h"
298 #include "ezr32lg_usb_doep.h"
299 #include "ezr32lg_usb.h"
300 #include "ezr32lg_msc.h"
301 #include "ezr32lg_emu.h"
302 #include "ezr32lg_rmu.h"
303 #include "ezr32lg_cmu.h"
304 #include "ezr32lg_lesense_st.h"
305 #include "ezr32lg_lesense_buf.h"
306 #include "ezr32lg_lesense_ch.h"
307 #include "ezr32lg_lesense.h"
308 #include "ezr32lg_usart.h"
309 #include "ezr32lg_timer_cc.h"
310 #include "ezr32lg_timer.h"
311 #include "ezr32lg_acmp.h"
312 #include "ezr32lg_leuart.h"
313 #include "ezr32lg_rtc.h"
314 #include "ezr32lg_letimer.h"
315 #include "ezr32lg_pcnt.h"
316 #include "ezr32lg_i2c.h"
317 #include "ezr32lg_gpio_p.h"
318 #include "ezr32lg_gpio.h"
319 #include "ezr32lg_vcmp.h"
320 #include "ezr32lg_prs_ch.h"
321 #include "ezr32lg_prs.h"
322 #include "ezr32lg_adc.h"
323 #include "ezr32lg_dac.h"
324 #include "ezr32lg_burtc_ret.h"
325 #include "ezr32lg_burtc.h"
326 #include "ezr32lg_wdog.h"
327 #include "ezr32lg_etm.h"
328 #include "ezr32lg_dma_descriptor.h"
329 #include "ezr32lg_devinfo.h"
330 #include "ezr32lg_romtable.h"
331 #include "ezr32lg_calibrate.h"
332 
335 /**************************************************************************/
340 #define DMA_BASE (0x400C2000UL)
341 #define AES_BASE (0x400E0000UL)
342 #define USB_BASE (0x400C4000UL)
343 #define MSC_BASE (0x400C0000UL)
344 #define EMU_BASE (0x400C6000UL)
345 #define RMU_BASE (0x400CA000UL)
346 #define CMU_BASE (0x400C8000UL)
347 #define LESENSE_BASE (0x4008C000UL)
348 #define USARTRF0_BASE (0x4000C000UL)
349 #define USART1_BASE (0x4000C400UL)
350 #define USART2_BASE (0x4000C800UL)
351 #define UART0_BASE (0x4000E000UL)
352 #define UART1_BASE (0x4000E400UL)
353 #define TIMER0_BASE (0x40010000UL)
354 #define TIMER1_BASE (0x40010400UL)
355 #define TIMER2_BASE (0x40010800UL)
356 #define TIMER3_BASE (0x40010C00UL)
357 #define ACMP0_BASE (0x40001000UL)
358 #define ACMP1_BASE (0x40001400UL)
359 #define LEUART0_BASE (0x40084000UL)
360 #define LEUART1_BASE (0x40084400UL)
361 #define RTC_BASE (0x40080000UL)
362 #define LETIMER0_BASE (0x40082000UL)
363 #define PCNT0_BASE (0x40086000UL)
364 #define PCNT1_BASE (0x40086400UL)
365 #define PCNT2_BASE (0x40086800UL)
366 #define I2C0_BASE (0x4000A000UL)
367 #define I2C1_BASE (0x4000A400UL)
368 #define GPIO_BASE (0x40006000UL)
369 #define VCMP_BASE (0x40000000UL)
370 #define PRS_BASE (0x400CC000UL)
371 #define ADC0_BASE (0x40002000UL)
372 #define DAC0_BASE (0x40004000UL)
373 #define BURTC_BASE (0x40081000UL)
374 #define WDOG_BASE (0x40088000UL)
375 #define ETM_BASE (0xE0041000UL)
376 #define CALIBRATE_BASE (0x0FE08000UL)
377 #define DEVINFO_BASE (0x0FE081A8UL)
378 #define ROMTABLE_BASE (0xE00FFFD0UL)
379 #define LOCKBITS_BASE (0x0FE04000UL)
380 #define USERDATA_BASE (0x0FE00000UL)
384 /**************************************************************************/
389 #define DMA ((DMA_TypeDef *) DMA_BASE)
390 #define AES ((AES_TypeDef *) AES_BASE)
391 #define USB ((USB_TypeDef *) USB_BASE)
392 #define MSC ((MSC_TypeDef *) MSC_BASE)
393 #define EMU ((EMU_TypeDef *) EMU_BASE)
394 #define RMU ((RMU_TypeDef *) RMU_BASE)
395 #define CMU ((CMU_TypeDef *) CMU_BASE)
396 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE)
397 #define USARTRF0 ((USART_TypeDef *) USARTRF0_BASE)
398 #define USART1 ((USART_TypeDef *) USART1_BASE)
399 #define USART2 ((USART_TypeDef *) USART2_BASE)
400 #define UART0 ((USART_TypeDef *) UART0_BASE)
401 #define UART1 ((USART_TypeDef *) UART1_BASE)
402 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
403 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
404 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
405 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE)
406 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
407 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
408 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
409 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
410 #define RTC ((RTC_TypeDef *) RTC_BASE)
411 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
412 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
413 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
414 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
415 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
416 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
417 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
418 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
419 #define PRS ((PRS_TypeDef *) PRS_BASE)
420 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
421 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
422 #define BURTC ((BURTC_TypeDef *) BURTC_BASE)
423 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
424 #define ETM ((ETM_TypeDef *) ETM_BASE)
425 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
426 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
427 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
431 /**************************************************************************/
436 #include "ezr32lg_prs_signals.h"
437 #include "ezr32lg_dmareq.h"
438 #include "ezr32lg_dmactrl.h"
439 #include "ezr32lg_usartrf.h"
440 #include "ezr32lg_uart.h"
441 
442 /**************************************************************************/
446 #define MSC_UNLOCK_CODE 0x1B71
447 #define EMU_UNLOCK_CODE 0xADE8
448 #define CMU_UNLOCK_CODE 0x580E
449 #define TIMER_UNLOCK_CODE 0xCE80
450 #define GPIO_UNLOCK_CODE 0xA534
451 #define BURTC_UNLOCK_CODE 0xAEE8
457 /**************************************************************************/
462 #include "ezr32lg_af_ports.h"
463 #include "ezr32lg_af_pins.h"
464 
467 /**************************************************************************/
480 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
481  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
482 
487 #ifdef __cplusplus
488 }
489 #endif
490 #endif /* EZR32LG330F256R69_H */
EZR32LG_BURTC register and bit field definitions.
EZR32LG_WDOG register and bit field definitions.
EZR32LG_DMA register and bit field definitions.
EZR32LG_DMA_DESCRIPTOR register and bit field definitions.
CMSIS Cortex-M3 System Layer for EZR32LG devices.
EZR32LG_AF_PINS register and bit field definitions.
EZR32LG_UART register and bit field definitions.
EZR32LG_TIMER_CC register and bit field definitions.
EZR32LG_DEVINFO register and bit field definitions.
EZR32LG_PCNT register and bit field definitions.
EZR32LG_LESENSE register and bit field definitions.
EZR32LG_ACMP register and bit field definitions.
EZR32LG_CMU register and bit field definitions.
EZR32LG_LESENSE_CH register and bit field definitions.
EZR32LG_ROMTABLE register and bit field definitions.
EZR32LG_BURTC_RET register and bit field definitions.
EZR32LG_LETIMER register and bit field definitions.
EZR32LG_USB_DOEP register and bit field definitions.
EZR32LG_EMU register and bit field definitions.
EZR32LG_DMAREQ register and bit field definitions.
EZR32LG_TIMER register and bit field definitions.
EZR32LG_ETM register and bit field definitions.
EZR32LG_GPIO register and bit field definitions.
EZR32LG_USB_HC register and bit field definitions.
EZR32LG_USB_DIEP register and bit field definitions.
EZR32LG_I2C register and bit field definitions.
EZR32LG_RMU register and bit field definitions.
EZR32LG_USART register and bit field definitions.
EZR32LG_CALIBRATE register and bit field definitions.
EZR32LG_ADC register and bit field definitions.
EZR32LG_PRS register and bit field definitions.
EZR32LG_LEUART register and bit field definitions.
EZR32LG_RTC register and bit field definitions.
EZR32LG_MSC register and bit field definitions.
EZR32LG_PRS_CH register and bit field definitions.
EZR32LG_VCMP register and bit field definitions.
EZR32LG_DMA_CH register and bit field definitions.
EZR32LG_USARTRF register and bit field definitions.
EZR32LG_LESENSE_BUF register and bit field definitions.
EZR32LG_GPIO_P register and bit field definitions.
EZR32LG_AES register and bit field definitions.
EZR32LG_DMACTRL register and bit field definitions.
EZR32LG_USB register and bit field definitions.
EZR32LG_DAC register and bit field definitions.
enum IRQn IRQn_Type
EZR32LG_LESENSE_ST register and bit field definitions.