33 #ifndef __SILICON_LABS_EM_CHIP_H__
34 #define __SILICON_LABS_EM_CHIP_H__
64 #if defined(_EFM32_GECKO_FAMILY)
67 volatile uint32_t *reg;
69 rev = *(
volatile uint32_t *)(0x0FE081FC);
73 reg = (
volatile uint32_t *)0x400CA00C;
76 reg = (
volatile uint32_t *)0x400C6020;
77 *reg &= ~(0xE0000000UL);
83 reg = (
volatile uint32_t *)0x400C6020;
84 *reg &= ~(0x00001F80UL);
86 reg = (
volatile uint32_t *)0x400C8040;
88 reg = (
volatile uint32_t *)0x400C8044;
90 reg = (
volatile uint32_t *)0x400C8058;
92 reg = (
volatile uint32_t *)0x400C8060;
94 reg = (
volatile uint32_t *)0x400C8078;
99 if (chipRev.
major == 0x01)
103 if (chipRev.
minor == 00)
105 reg = (
volatile uint32_t *)0x400C8040;
112 if (chipRev.
minor <= 0x01)
114 reg = (
volatile uint32_t *)0x400C8044;
119 rev = *(
volatile uint32_t *)0x0FE081F0;
120 if (rev < 0x4C8ABA00)
125 reg = (
volatile uint32_t *)0x400C8044UL;
126 *reg |= (1 << 14 | 1 << 11);
129 cal = ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
132 cal |= ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
135 cal |= ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
138 cal |= ((*(
volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
142 reg = (
volatile uint32_t *)0x40002034UL;
146 reg = (
volatile uint32_t *)(0x4000402CUL);
147 cal = *(
volatile uint32_t *)0x0FE081C8UL;
151 reg = (
volatile uint32_t *)0x400C8044UL;
152 *reg &= ~(1 << 14 | 1 << 11);
156 #if defined(_EFM32_GIANT_FAMILY)
160 rev = *(
volatile uint32_t *)(0x0FE081FC);
163 if (((rev >> 24) > 15) && (chipRev.
minor == 3))
166 *(
volatile uint32_t*)0x400C80C0 =
167 ( *(
volatile uint32_t*)0x400C80C0 & ~(1<<6) ) | (1<<4);
171 #if defined(_EFM32_HAPPY_FAMILY)
173 rev = *(
volatile uint32_t *)(0x0FE081FC);
175 if ((rev >> 24) <= 129)
179 *(
volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
181 *(
volatile uint32_t*)(0x400C80E4) &= ~(1 << 24);
void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
Get chip major/minor revision.
__STATIC_INLINE void CHIP_Init(void)
Chip initialization routine for revision errata workarounds.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.