00001
00035 #ifndef __SILICON_LABS_EM_DMA_H_
00036 #define __SILICON_LABS_EM_DMA_H_
00037
00038 #include "em_device.h"
00039 #if defined( DMA_PRESENT )
00040
00041 #include <stdio.h>
00042 #include <stdbool.h>
00043
00044 #ifdef __cplusplus
00045 extern "C" {
00046 #endif
00047
00048
00053
00058
00059
00060
00061
00066 typedef enum
00067 {
00068 dmaDataInc1 = _DMA_CTRL_SRC_INC_BYTE,
00069 dmaDataInc2 = _DMA_CTRL_SRC_INC_HALFWORD,
00070 dmaDataInc4 = _DMA_CTRL_SRC_INC_WORD,
00071 dmaDataIncNone = _DMA_CTRL_SRC_INC_NONE
00072 } DMA_DataInc_TypeDef;
00073
00074
00076 typedef enum
00077 {
00078 dmaDataSize1 = _DMA_CTRL_SRC_SIZE_BYTE,
00079 dmaDataSize2 = _DMA_CTRL_SRC_SIZE_HALFWORD,
00080 dmaDataSize4 = _DMA_CTRL_SRC_SIZE_WORD
00081 } DMA_DataSize_TypeDef;
00082
00083
00085 typedef enum
00086 {
00088 dmaCycleCtrlBasic = _DMA_CTRL_CYCLE_CTRL_BASIC,
00090 dmaCycleCtrlAuto = _DMA_CTRL_CYCLE_CTRL_AUTO,
00092 dmaCycleCtrlPingPong = _DMA_CTRL_CYCLE_CTRL_PINGPONG,
00094 dmaCycleCtrlMemScatterGather = _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER,
00096 dmaCycleCtrlPerScatterGather = _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER
00097 } DMA_CycleCtrl_TypeDef;
00098
00099
00101 typedef enum
00102 {
00103 dmaArbitrate1 = _DMA_CTRL_R_POWER_1,
00104 dmaArbitrate2 = _DMA_CTRL_R_POWER_2,
00105 dmaArbitrate4 = _DMA_CTRL_R_POWER_4,
00106 dmaArbitrate8 = _DMA_CTRL_R_POWER_8,
00107 dmaArbitrate16 = _DMA_CTRL_R_POWER_16,
00108 dmaArbitrate32 = _DMA_CTRL_R_POWER_32,
00109 dmaArbitrate64 = _DMA_CTRL_R_POWER_64,
00110 dmaArbitrate128 = _DMA_CTRL_R_POWER_128,
00111 dmaArbitrate256 = _DMA_CTRL_R_POWER_256,
00112 dmaArbitrate512 = _DMA_CTRL_R_POWER_512,
00113 dmaArbitrate1024 = _DMA_CTRL_R_POWER_1024
00114 } DMA_ArbiterConfig_TypeDef;
00115
00116
00117
00118
00119
00120
00137 typedef void (*DMA_FuncPtr_TypeDef)(unsigned int channel, bool primary, void *user);
00138
00139
00150 typedef struct
00151 {
00157 DMA_FuncPtr_TypeDef cbFunc;
00158
00160 void *userPtr;
00161
00167 uint8_t primary;
00168 } DMA_CB_TypeDef;
00169
00170
00172 typedef struct
00173 {
00179 bool highPri;
00180
00187 bool enableInt;
00188
00194 uint32_t select;
00195
00210 DMA_CB_TypeDef *cb;
00211 } DMA_CfgChannel_TypeDef;
00212
00213
00218 typedef struct
00219 {
00221 DMA_DataInc_TypeDef dstInc;
00222
00224 DMA_DataInc_TypeDef srcInc;
00225
00227 DMA_DataSize_TypeDef size;
00228
00233 DMA_ArbiterConfig_TypeDef arbRate;
00234
00244 uint8_t hprot;
00245 } DMA_CfgDescr_TypeDef;
00246
00247
00248 #if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
00249
00252 typedef struct
00253 {
00255 bool enable;
00257 uint16_t nMinus1;
00258 } DMA_CfgLoop_TypeDef;
00259 #endif
00260
00261
00262 #if defined( _DMA_RECT0_MASK )
00263
00266 typedef struct
00267 {
00269 uint16_t dstStride;
00271 uint16_t srcStride;
00273 uint16_t height;
00274 } DMA_CfgRect_TypeDef;
00275 #endif
00276
00277
00279 typedef struct
00280 {
00282 void *src;
00283
00285 void *dst;
00286
00288 DMA_DataInc_TypeDef dstInc;
00289
00291 DMA_DataInc_TypeDef srcInc;
00292
00294 DMA_DataSize_TypeDef size;
00295
00300 DMA_ArbiterConfig_TypeDef arbRate;
00301
00303 uint16_t nMinus1;
00304
00314 uint8_t hprot;
00315
00322 bool peripheral;
00323 } DMA_CfgDescrSGAlt_TypeDef;
00324
00325
00327 typedef struct
00328 {
00337 uint8_t hprot;
00338
00354 DMA_DESCRIPTOR_TypeDef *controlBlock;
00355 } DMA_Init_TypeDef;
00356
00357
00358
00359
00360
00361
00362 void DMA_ActivateAuto(unsigned int channel,
00363 bool primary,
00364 void *dst,
00365 void *src,
00366 unsigned int nMinus1);
00367 void DMA_ActivateBasic(unsigned int channel,
00368 bool primary,
00369 bool useBurst,
00370 void *dst,
00371 void *src,
00372 unsigned int nMinus1);
00373 void DMA_ActivatePingPong(unsigned int channel,
00374 bool useBurst,
00375 void *primDst,
00376 void *primSrc,
00377 unsigned int primNMinus1,
00378 void *altDst,
00379 void *altSrc,
00380 unsigned int altNMinus1);
00381 void DMA_ActivateScatterGather(unsigned int channel,
00382 bool useBurst,
00383 DMA_DESCRIPTOR_TypeDef *altDescr,
00384 unsigned int count);
00385 void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg);
00386 void DMA_CfgDescr(unsigned int channel,
00387 bool primary,
00388 DMA_CfgDescr_TypeDef *cfg);
00389 #if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
00390 void DMA_CfgLoop(unsigned int channel, DMA_CfgLoop_TypeDef *cfg);
00391 #endif
00392
00393 #if defined( _DMA_RECT0_MASK )
00394 void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg);
00395 #endif
00396
00397 #if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
00398
00405 __STATIC_INLINE void DMA_ResetLoop(unsigned int channel)
00406 {
00407
00408 switch(channel)
00409 {
00410 case 0:
00411 DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;
00412 break;
00413 case 1:
00414 DMA->LOOP1 = _DMA_LOOP1_RESETVALUE;
00415 break;
00416 default:
00417 break;
00418 }
00419 }
00420 #endif
00421
00422
00423 #if defined( _DMA_RECT0_MASK )
00424
00431 __STATIC_INLINE void DMA_ResetRect(unsigned int channel)
00432 {
00433 (void) channel;
00434
00435
00436 DMA->RECT0 = _DMA_RECT0_RESETVALUE;
00437 }
00438 #endif
00439 void DMA_CfgDescrScatterGather(DMA_DESCRIPTOR_TypeDef *descr,
00440 unsigned int indx,
00441 DMA_CfgDescrSGAlt_TypeDef *cfg);
00442 void DMA_ChannelEnable(unsigned int channel, bool enable);
00443 bool DMA_ChannelEnabled(unsigned int channel);
00444 void DMA_Init(DMA_Init_TypeDef *init);
00445 void DMA_IRQHandler(void);
00446 void DMA_RefreshPingPong(unsigned int channel,
00447 bool primary,
00448 bool useBurst,
00449 void *dst,
00450 void *src,
00451 unsigned int nMinus1,
00452 bool last);
00453 void DMA_Reset(void);
00454
00458 #ifdef __cplusplus
00459 }
00460 #endif
00461
00462 #endif
00463 #endif