EZR32 Wonder Gecko Software Documentation  ezr32wg-doc-4.2.1
em_ebi.c
Go to the documentation of this file.
1 /***************************************************************************/
33 #include "em_ebi.h"
34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
35 #include "em_assert.h"
36 #include "em_bus.h"
37 
38 /***************************************************************************/
43 /***************************************************************************/
49 /***************************************************************************/
60 void EBI_Init(const EBI_Init_TypeDef *ebiInit)
61 {
62  uint32_t ctrl = EBI->CTRL;
63 
64 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
65  /* Enable Independent Timing for devices that supports it */
66  ctrl |= EBI_CTRL_ITS;
67 
68  /* Set polarity of address ready */
69  EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
70  /* Set polarity of address latch enable */
71  EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
72  /* Set polarity of write enable */
73  EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
74  /* Set polarity of read enable */
75  EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
76  /* Set polarity of chip select lines */
77  EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
78  /* Set polarity of byte lane line */
79  EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
80 #else
81  /* Set polarity of address ready */
82  EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
83  /* Set polarity of address latch enable */
84  EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
85  /* Set polarity of write enable */
86  EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
87  /* Set polarity of read enable */
88  EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
89  /* Set polarity of chip select lines */
90  EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
91 #endif
92 
93  /* Configure EBI mode and control settings */
94 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
95  if (ebiInit->banks & EBI_BANK0)
96  {
97  ctrl &= ~(_EBI_CTRL_MODE_MASK
98  | _EBI_CTRL_ARDYEN_MASK
99  | _EBI_CTRL_ARDYTODIS_MASK
100  | _EBI_CTRL_BL_MASK
101  | _EBI_CTRL_NOIDLE_MASK
102  | _EBI_CTRL_BANK0EN_MASK);
103  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
104  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
105  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
106  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
107  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
108  if ( ebiInit->enable)
109  {
110  ctrl |= EBI_CTRL_BANK0EN;
111  }
112  }
113  if (ebiInit->banks & EBI_BANK1)
114  {
115  ctrl &= ~(_EBI_CTRL_BL1_MASK
116  | _EBI_CTRL_MODE1_MASK
117  | _EBI_CTRL_ARDY1EN_MASK
118  | _EBI_CTRL_ARDYTO1DIS_MASK
119  | _EBI_CTRL_NOIDLE1_MASK
120  | _EBI_CTRL_BANK1EN_MASK);
121  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
122  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
123  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
124  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
125  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
126  if ( ebiInit->enable)
127  {
128  ctrl |= EBI_CTRL_BANK1EN;
129  }
130  }
131  if (ebiInit->banks & EBI_BANK2)
132  {
133  ctrl &= ~(_EBI_CTRL_BL2_MASK
134  | _EBI_CTRL_MODE2_MASK
135  | _EBI_CTRL_ARDY2EN_MASK
136  | _EBI_CTRL_ARDYTO2DIS_MASK
137  | _EBI_CTRL_NOIDLE2_MASK
138  | _EBI_CTRL_BANK2EN_MASK);
139  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
140  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
141  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
142  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
143  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
144  if ( ebiInit->enable)
145  {
146  ctrl |= EBI_CTRL_BANK2EN;
147  }
148  }
149  if (ebiInit->banks & EBI_BANK3)
150  {
151  ctrl &= ~(_EBI_CTRL_BL3_MASK
152  | _EBI_CTRL_MODE3_MASK
153  | _EBI_CTRL_ARDY3EN_MASK
154  | _EBI_CTRL_ARDYTO3DIS_MASK
155  | _EBI_CTRL_NOIDLE3_MASK
156  | _EBI_CTRL_BANK3EN_MASK);
157  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
158  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
159  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
160  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
161  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
162  if ( ebiInit->enable)
163  {
164  ctrl |= EBI_CTRL_BANK3EN;
165  }
166  }
167 #else
168  ctrl &= ~(_EBI_CTRL_MODE_MASK
169  | _EBI_CTRL_ARDYEN_MASK
170  | _EBI_CTRL_ARDYTODIS_MASK
171  | _EBI_CTRL_BANK0EN_MASK
172  | _EBI_CTRL_BANK1EN_MASK
173  | _EBI_CTRL_BANK2EN_MASK
174  | _EBI_CTRL_BANK3EN_MASK);
175  if ( ebiInit->enable)
176  {
177  if ( ebiInit->banks & EBI_BANK0 )
178  {
179  ctrl |= EBI_CTRL_BANK0EN;
180  }
181  if ( ebiInit->banks & EBI_BANK1 )
182  {
183  ctrl |= EBI_CTRL_BANK1EN;
184  }
185  if ( ebiInit->banks & EBI_BANK2 )
186  {
187  ctrl |= EBI_CTRL_BANK2EN;
188  }
189  if ( ebiInit->banks & EBI_BANK3 )
190  {
191  ctrl |= EBI_CTRL_BANK3EN;
192  }
193  }
194  ctrl |= ebiInit->mode;
195  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
196  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
197 #endif
198 
199  /* Configure timing */
200 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
201  EBI_BankReadTimingSet(ebiInit->banks,
202  ebiInit->readSetupCycles,
203  ebiInit->readStrobeCycles,
204  ebiInit->readHoldCycles);
205  EBI_BankReadTimingConfig(ebiInit->banks,
206  ebiInit->readPageMode,
207  ebiInit->readPrefetch,
208  ebiInit->readHalfRE);
209  EBI_BankWriteTimingSet(ebiInit->banks,
210  ebiInit->writeSetupCycles,
211  ebiInit->writeStrobeCycles,
212  ebiInit->writeHoldCycles);
213  EBI_BankWriteTimingConfig(ebiInit->banks,
214  ebiInit->writeBufferDisable,
215  ebiInit->writeHalfWE);
216  EBI_BankAddressTimingSet(ebiInit->banks,
217  ebiInit->addrSetupCycles,
218  ebiInit->addrHoldCycles);
219  EBI_BankAddressTimingConfig(ebiInit->banks,
220  ebiInit->addrHalfALE);
221 #else
222  EBI_ReadTimingSet(ebiInit->readSetupCycles,
223  ebiInit->readStrobeCycles,
224  ebiInit->readHoldCycles);
225  EBI_WriteTimingSet(ebiInit->writeSetupCycles,
226  ebiInit->writeStrobeCycles,
227  ebiInit->writeHoldCycles);
228  EBI_AddressTimingSet(ebiInit->addrSetupCycles,
229  ebiInit->addrHoldCycles);
230 #endif
231 
232  /* Activate new configuration */
233  EBI->CTRL = ctrl;
234 
235  /* Configure Adress Latch Enable */
236  switch (ebiInit->mode)
237  {
238  case ebiModeD16A16ALE:
239  case ebiModeD8A24ALE:
240  /* Address Latch Enable */
241  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
242  break;
243 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
244  case ebiModeD16:
245 #endif
246  case ebiModeD8A8:
247  /* Make sure Address Latch is disabled */
248  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
249  break;
250  }
251 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
252  /* Limit pin enable */
253  EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
254  EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
255  /* Location */
256  EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
257 
258  /* Enable EBI BL pin if necessary */
259  if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
260  {
261  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
262  }
263 #endif
264  /* Enable EBI pins EBI_WEn and EBI_REn */
265  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
266 
267  /* Enable chip select lines */
268  EBI_ChipSelectEnable(ebiInit->csLines, true);
269 }
270 
271 
272 /***************************************************************************/
276 void EBI_Disable(void)
277 {
278  /* Disable pins */
279  EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
280  /* Disable banks */
281  EBI->CTRL = _EBI_CTRL_RESETVALUE;
282 }
283 
284 
285 /***************************************************************************/
295 void EBI_BankEnable(uint32_t banks, bool enable)
296 {
297  if (banks & EBI_BANK0)
298  {
299  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
300  }
301  if (banks & EBI_BANK1)
302  {
303  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
304  }
305  if (banks & EBI_BANK2)
306  {
307  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
308  }
309  if (banks & EBI_BANK3)
310  {
311  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
312  }
313 }
314 
315 
316 /***************************************************************************/
326 uint32_t EBI_BankAddress(uint32_t bank)
327 {
328 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
329  if(EBI->CTRL & EBI_CTRL_ALTMAP)
330  {
331  switch (bank)
332  {
333  case EBI_BANK0:
334  return(EBI_MEM_BASE);
335 
336  case EBI_BANK1:
337  return(EBI_MEM_BASE + 0x10000000UL);
338 
339  case EBI_BANK2:
340  return(EBI_MEM_BASE + 0x20000000UL);
341 
342  case EBI_BANK3:
343  return(EBI_MEM_BASE + 0x30000000UL);
344 
345  default:
346  EFM_ASSERT(0);
347  break;
348  }
349  }
350 #endif
351  switch (bank)
352  {
353  case EBI_BANK0:
354  return(EBI_MEM_BASE);
355 
356  case EBI_BANK1:
357  return(EBI_MEM_BASE + 0x04000000UL);
358 
359  case EBI_BANK2:
360  return(EBI_MEM_BASE + 0x08000000UL);
361 
362  case EBI_BANK3:
363  return(EBI_MEM_BASE + 0x0C000000UL);
364 
365  default:
366  EFM_ASSERT(0);
367  break;
368  }
369  return 0;
370 }
371 
372 
373 /***************************************************************************/
383 void EBI_ChipSelectEnable(uint32_t cs, bool enable)
384 {
385  if (cs & EBI_CS0)
386  {
387  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
388  }
389  if (cs & EBI_CS1)
390  {
391  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
392  }
393  if (cs & EBI_CS2)
394  {
395  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
396  }
397  if (cs & EBI_CS3)
398  {
399  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
400  }
401 }
402 
403 
404 /***************************************************************************/
414 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
415 {
416  switch (line)
417  {
418  case ebiLineARDY:
419  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
420  break;
421  case ebiLineALE:
422  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
423  break;
424  case ebiLineWE:
425  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
426  break;
427  case ebiLineRE:
428  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
429  break;
430  case ebiLineCS:
431  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
432  break;
433 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
434  case ebiLineBL:
435  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
436  break;
437  case ebiLineTFTVSync:
438  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
439  break;
440  case ebiLineTFTHSync:
441  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
442  break;
443  case ebiLineTFTDataEn:
444  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
445  break;
446  case ebiLineTFTDClk:
447  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
448  break;
449  case ebiLineTFTCS:
450  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
451  break;
452 #endif
453  default:
454  EFM_ASSERT(0);
455  break;
456  }
457 }
458 
459 
460 /***************************************************************************/
474 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
475 {
476  uint32_t readTiming;
477 
478  /* Check that timings are within limits */
479  EFM_ASSERT(setupCycles < 4);
480  EFM_ASSERT(strobeCycles < 16);
481  EFM_ASSERT(holdCycles < 4);
482 
483  /* Configure timing values */
484  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
485  | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
486  | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
487 
488 
489  EBI->RDTIMING = (EBI->RDTIMING
490  & ~(_EBI_RDTIMING_RDSETUP_MASK
491  | _EBI_RDTIMING_RDSTRB_MASK
492  | _EBI_RDTIMING_RDHOLD_MASK))
493  | readTiming;
494 }
495 
496 
497 /***************************************************************************/
510 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
511 {
512  uint32_t writeTiming;
513 
514  /* Check that timings are within limits */
515  EFM_ASSERT(setupCycles < 4);
516  EFM_ASSERT(strobeCycles < 16);
517  EFM_ASSERT(holdCycles < 4);
518 
519  /* Configure timing values */
520  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
521  | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
522  | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
523 
524  EBI->WRTIMING = (EBI->WRTIMING
525  & ~(_EBI_WRTIMING_WRSETUP_MASK
526  | _EBI_WRTIMING_WRSTRB_MASK
527  | _EBI_WRTIMING_WRHOLD_MASK))
528  | writeTiming;
529 }
530 
531 
532 /***************************************************************************/
543 void EBI_AddressTimingSet(int setupCycles, int holdCycles)
544 {
545  uint32_t addressLatchTiming;
546 
547  /* Check that timing values are within limits */
548  EFM_ASSERT(setupCycles < 4);
549  EFM_ASSERT(holdCycles < 4);
550 
551  /* Configure address latch timing values */
552  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
553  | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
554 
555  EBI->ADDRTIMING = (EBI->ADDRTIMING
556  & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
557  | _EBI_ADDRTIMING_ADDRHOLD_MASK))
558  | addressLatchTiming;
559 }
560 
561 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
562 /***************************************************************************/
569 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
570 {
571  uint32_t ctrl;
572 
573  /* Configure base address for frame buffer offset to EBI bank */
574  EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
575 
576  /* Configure display size and porch areas */
577  EBI_TFTSizeSet(ebiTFTInit->hsize,
578  ebiTFTInit->vsize);
579  EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
580  ebiTFTInit->hPorchBack,
581  ebiTFTInit->hPulseWidth);
582  EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
583  ebiTFTInit->vPorchBack,
584  ebiTFTInit->vPulseWidth);
585 
586  /* Configure timing settings */
587  EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
588  ebiTFTInit->startPosition,
589  ebiTFTInit->setupCycles,
590  ebiTFTInit->holdCycles);
591 
592  /* Configure line polarity settings */
593  EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
594  EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
595  EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
596  EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
597  EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
598 
599  /* Main control, EBI bank select, mask and blending configuration */
600  ctrl = (uint32_t)ebiTFTInit->bank
601  | (uint32_t)ebiTFTInit->width
602  | (uint32_t)ebiTFTInit->colSrc
603  | (uint32_t)ebiTFTInit->interleave
604  | (uint32_t)ebiTFTInit->fbTrigger
605  | (uint32_t)(ebiTFTInit->shiftDClk == true
606  ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
607  | (uint32_t)ebiTFTInit->maskBlend
608  | (uint32_t)ebiTFTInit->driveMode;
609 
610  EBI->TFTCTRL = ctrl;
611 
612  /* Enable TFT pins */
613  if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
614  {
615  EBI->ROUTE |= EBI_ROUTE_TFTPEN;
616  }
617 }
618 
619 
620 /***************************************************************************/
629 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
630 {
631  EFM_ASSERT((horizontal-1) < 1024);
632  EFM_ASSERT((vertical-1) < 1024);
633 
634  EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
635  | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
636 }
637 
638 /***************************************************************************/
649 void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
650 {
651  EFM_ASSERT(front < 256);
652  EFM_ASSERT(back < 256);
653  EFM_ASSERT((pulseWidth-1) < 128);
654 
655  EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
656  | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
657  | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
658 }
659 
660 
661 /***************************************************************************/
672 void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
673 {
674  EFM_ASSERT(front < 256);
675  EFM_ASSERT(back < 256);
676  EFM_ASSERT((pulseWidth-1) < 128);
677 
678  EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
679  | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
680  | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
681 }
682 
683 
684 /***************************************************************************/
700 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
701 {
702  EFM_ASSERT(dclkPeriod < 2048);
703  EFM_ASSERT(start < 2048);
704  EFM_ASSERT(setup < 4);
705  EFM_ASSERT(hold < 4);
706 
707  EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
708  | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
709  | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
710  | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
711 }
712 #endif
713 
714 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
715 /***************************************************************************/
731 void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
732 {
733  /* Verify only valid banks are used */
734  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
735 
736  /* Configure read operation parameters */
737  if( banks & EBI_BANK0 )
738  {
739  BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
740  BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
741  BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
742  }
743  if( banks & EBI_BANK1 )
744  {
745  BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
746  BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
747  BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
748  }
749  if( banks & EBI_BANK2 )
750  {
751  BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
752  BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
753  BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
754  }
755  if( banks & EBI_BANK3 )
756  {
757  BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
758  BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
759  BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
760  }
761 }
762 
763 /***************************************************************************/
780 void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
781 {
782  uint32_t readTiming;
783 
784  /* Verify only valid banks are used */
785  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
786 
787  /* Check that timings are within limits */
788  EFM_ASSERT(setupCycles < 4);
789  EFM_ASSERT(strobeCycles < 64);
790  EFM_ASSERT(holdCycles < 4);
791 
792  /* Configure timing values */
793  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
794  | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
795  | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
796 
797  if (banks & EBI_BANK0)
798  {
799  EBI->RDTIMING = (EBI->RDTIMING
800  & ~(_EBI_RDTIMING_RDSETUP_MASK
801  | _EBI_RDTIMING_RDSTRB_MASK
802  | _EBI_RDTIMING_RDHOLD_MASK))
803  | readTiming;
804  }
805  if (banks & EBI_BANK1)
806  {
807  EBI->RDTIMING1 = (EBI->RDTIMING1
808  & ~(_EBI_RDTIMING1_RDSETUP_MASK
809  | _EBI_RDTIMING1_RDSTRB_MASK
810  | _EBI_RDTIMING1_RDHOLD_MASK))
811  | readTiming;
812  }
813  if (banks & EBI_BANK2)
814  {
815  EBI->RDTIMING2 = (EBI->RDTIMING2
816  & ~(_EBI_RDTIMING2_RDSETUP_MASK
817  | _EBI_RDTIMING2_RDSTRB_MASK
818  | _EBI_RDTIMING2_RDHOLD_MASK))
819  | readTiming;
820  }
821  if (banks & EBI_BANK3)
822  {
823  EBI->RDTIMING3 = (EBI->RDTIMING3
824  & ~(_EBI_RDTIMING3_RDSETUP_MASK
825  | _EBI_RDTIMING3_RDSTRB_MASK
826  | _EBI_RDTIMING3_RDHOLD_MASK))
827  | readTiming;
828  }
829 }
830 
831 
832 /***************************************************************************/
845 void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
846 {
847  /* Verify only valid banks are used */
848  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
849 
850  /* Configure write operation parameters */
851  if( banks & EBI_BANK0 )
852  {
853  BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
854  BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
855  }
856  if( banks & EBI_BANK1 )
857  {
858  BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
859  BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
860  }
861  if( banks & EBI_BANK2 )
862  {
863  BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
864  BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
865  }
866  if( banks & EBI_BANK3 )
867  {
868  BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
869  BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
870  }
871 }
872 
873 
874 /***************************************************************************/
890 void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
891 {
892  uint32_t writeTiming;
893 
894  /* Verify only valid banks are used */
895  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
896 
897  /* Check that timings are within limits */
898  EFM_ASSERT(setupCycles < 4);
899  EFM_ASSERT(strobeCycles < 64);
900  EFM_ASSERT(holdCycles < 4);
901 
902  /* Configure timing values */
903  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
904  | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
905  | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
906 
907  if (banks & EBI_BANK0)
908  {
909  EBI->WRTIMING = (EBI->WRTIMING
910  & ~(_EBI_WRTIMING_WRSETUP_MASK
911  | _EBI_WRTIMING_WRSTRB_MASK
912  | _EBI_WRTIMING_WRHOLD_MASK))
913  | writeTiming;
914  }
915  if (banks & EBI_BANK1)
916  {
917  EBI->WRTIMING1 = (EBI->WRTIMING1
918  & ~(_EBI_WRTIMING1_WRSETUP_MASK
919  | _EBI_WRTIMING1_WRSTRB_MASK
920  | _EBI_WRTIMING1_WRHOLD_MASK))
921  | writeTiming;
922  }
923  if (banks & EBI_BANK2)
924  {
925  EBI->WRTIMING2 = (EBI->WRTIMING2
926  & ~(_EBI_WRTIMING2_WRSETUP_MASK
927  | _EBI_WRTIMING2_WRSTRB_MASK
928  | _EBI_WRTIMING2_WRHOLD_MASK))
929  | writeTiming;
930  }
931  if (banks & EBI_BANK3)
932  {
933  EBI->WRTIMING3 = (EBI->WRTIMING3
934  & ~(_EBI_WRTIMING3_WRSETUP_MASK
935  | _EBI_WRTIMING3_WRSTRB_MASK
936  | _EBI_WRTIMING3_WRHOLD_MASK))
937  | writeTiming;
938  }
939 }
940 
941 
942 /***************************************************************************/
952 void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
953 {
954  /* Verify only valid banks are used */
955  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
956 
957  if( banks & EBI_BANK0 )
958  {
959  BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
960  }
961  if( banks & EBI_BANK1 )
962  {
963  BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
964  }
965  if( banks & EBI_BANK2 )
966  {
967  BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
968  }
969  if( banks & EBI_BANK3 )
970  {
971  BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
972  }
973 }
974 
975 
976 /***************************************************************************/
990 void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
991 {
992  uint32_t addressLatchTiming;
993 
994  /* Verify only valid banks are used */
995  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
996 
997  /* Check that timing values are within limits */
998  EFM_ASSERT(setupCycles < 4);
999  EFM_ASSERT(holdCycles < 4);
1000 
1001  /* Configure address latch timing values */
1002  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
1003  | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
1004 
1005  if (banks & EBI_BANK0)
1006  {
1007  EBI->ADDRTIMING = (EBI->ADDRTIMING
1008  & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
1009  | _EBI_ADDRTIMING_ADDRHOLD_MASK))
1010  | addressLatchTiming;
1011  }
1012  if (banks & EBI_BANK1)
1013  {
1014  EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
1015  & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
1016  | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
1017  | addressLatchTiming;
1018  }
1019  if (banks & EBI_BANK2)
1020  {
1021  EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
1022  & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
1023  | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
1024  | addressLatchTiming;
1025  }
1026  if (banks & EBI_BANK3)
1027  {
1028  EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
1029  & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
1030  | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
1031  | addressLatchTiming;
1032  }
1033 }
1034 
1035 
1036 /***************************************************************************/
1050 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
1051 {
1052  uint32_t bankSet = 0;
1053  volatile uint32_t *polRegister = 0;
1054 
1055  /* Verify only valid banks are used */
1056  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1057 
1058  while (banks)
1059  {
1060 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1061  if (banks & EBI_BANK0)
1062  {
1063  polRegister = &EBI->POLARITY;
1064  bankSet = EBI_BANK0;
1065  }
1066  if (banks & EBI_BANK1)
1067  {
1068  polRegister = &EBI->POLARITY1;
1069  bankSet = EBI_BANK1;
1070  }
1071  if (banks & EBI_BANK2)
1072  {
1073  polRegister = &EBI->POLARITY2;
1074  bankSet = EBI_BANK2;
1075  }
1076  if (banks & EBI_BANK3)
1077  {
1078  polRegister = &EBI->POLARITY3;
1079  bankSet = EBI_BANK3;
1080  }
1081 #else
1082  polRegister = &EBI->POLARITY;
1083  banks = 0;
1084 #endif
1085 
1086  /* What line to configure */
1087  switch (line)
1088  {
1089  case ebiLineARDY:
1090  BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
1091  break;
1092  case ebiLineALE:
1093  BUS_RegBitWrite(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
1094  break;
1095  case ebiLineWE:
1096  BUS_RegBitWrite(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
1097  break;
1098  case ebiLineRE:
1099  BUS_RegBitWrite(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
1100  break;
1101  case ebiLineCS:
1102  BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
1103  break;
1104 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1105  case ebiLineBL:
1106  BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
1107  break;
1108  case ebiLineTFTVSync:
1109  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
1110  break;
1111  case ebiLineTFTHSync:
1112  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
1113  break;
1114  case ebiLineTFTDataEn:
1115  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
1116  break;
1117  case ebiLineTFTDClk:
1118  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
1119  break;
1120  case ebiLineTFTCS:
1121  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
1122  break;
1123 #endif
1124  default:
1125  EFM_ASSERT(0);
1126  break;
1127  }
1128  banks = banks & ~bankSet;
1129  }
1130 }
1131 
1132 
1133 /***************************************************************************/
1144 void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
1145 {
1146  /* Verify only valid banks are used */
1147  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1148 
1149  /* Configure byte lane support for each selected bank */
1150  if (banks & EBI_BANK0)
1151  {
1152  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
1153  }
1154  if (banks & EBI_BANK1)
1155  {
1156  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
1157  }
1158  if (banks & EBI_BANK2)
1159  {
1160  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
1161  }
1162  if (banks & EBI_BANK3)
1163  {
1164  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
1165  }
1166 }
1167 
1168 
1169 /***************************************************************************/
1177 void EBI_AltMapEnable(bool enable)
1178 {
1179  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
1180 }
1181 
1182 #endif
1183 
1187 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */
Emlib peripheral API "assert" implementation.
RAM and peripheral bit-field set and clear API.
External Bus Iterface (EBI) peripheral API.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146