EZR32 Wonder Gecko Software Documentation  ezr32wg-doc-4.2.1
em_dma.c
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1 /***************************************************************************/
33 #include "em_dma.h"
34 #if defined( DMA_PRESENT )
35 
36 #include "em_cmu.h"
37 #include "em_assert.h"
38 #include "em_bus.h"
39 
40 /***************************************************************************/
45 /***************************************************************************/
124 /*******************************************************************************
125  ************************** LOCAL FUNCTIONS ********************************
126  ******************************************************************************/
127 
130 /***************************************************************************/
171 static void DMA_Prepare(unsigned int channel,
172  DMA_CycleCtrl_TypeDef cycleCtrl,
173  bool primary,
174  bool useBurst,
175  void *dst,
176  void *src,
177  unsigned int nMinus1)
178 {
179  DMA_DESCRIPTOR_TypeDef *descr;
180  DMA_DESCRIPTOR_TypeDef *primDescr;
181  DMA_CB_TypeDef *cb;
182  uint32_t inc;
183  uint32_t chBit;
184  uint32_t tmp;
185 
186  primDescr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;
187 
188  /* Find descriptor to configure */
189  if (primary)
190  {
191  descr = primDescr;
192  }
193  else
194  {
195  descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;
196  }
197 
198  /* If callback defined, update info on whether callback is issued */
199  /* for primary or alternate descriptor. Mainly needed for ping-pong */
200  /* cycles. */
201  cb = (DMA_CB_TypeDef *)(primDescr->USER);
202  if (cb)
203  {
204  cb->primary = (uint8_t)primary;
205  }
206 
207  if (src)
208  {
210  if (inc == _DMA_CTRL_SRC_INC_NONE)
211  {
212  descr->SRCEND = src;
213  }
214  else
215  {
216  descr->SRCEND = (void *)((uint32_t)src + (nMinus1 << inc));
217  }
218  }
219 
220  if (dst)
221  {
223  if (inc == _DMA_CTRL_DST_INC_NONE)
224  {
225  descr->DSTEND = dst;
226  }
227  else
228  {
229  descr->DSTEND = (void *)((uint32_t)dst + (nMinus1 << inc));
230  }
231  }
232 
233  chBit = 1 << channel;
234  if (useBurst)
235  {
236  DMA->CHUSEBURSTS = chBit;
237  }
238  else
239  {
240  DMA->CHUSEBURSTC = chBit;
241  }
242 
243  if (primary)
244  {
245  DMA->CHALTC = chBit;
246  }
247  else
248  {
249  DMA->CHALTS = chBit;
250  }
251 
252  /* Set cycle control */
254  tmp |= nMinus1 << _DMA_CTRL_N_MINUS_1_SHIFT;
255  tmp |= (uint32_t)cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT;
256  descr->CTRL = tmp;
257 }
258 
261 /*******************************************************************************
262  ************************ INTERRUPT FUNCTIONS ******************************
263  ******************************************************************************/
264 
265 #ifndef EXCLUDE_DEFAULT_DMA_IRQ_HANDLER
266 
267 /***************************************************************************/
284 void DMA_IRQHandler(void)
285 {
286  int channel;
287  DMA_CB_TypeDef *cb;
288  uint32_t pending;
289  uint32_t pendingPrio;
290  uint32_t prio;
291  uint32_t primaryCpy;
292  int i;
293 
294  /* Get all pending and enabled interrupts */
295  pending = DMA->IF;
296  pending &= DMA->IEN;
297 
298  /* Check for bus error */
299  if (pending & DMA_IF_ERR)
300  {
301  /* Loop here to enable the debugger to see what has happened */
302  while (1)
303  ;
304  }
305 
306  /* Process all pending channel interrupts. First process channels */
307  /* defined with high priority, then those with default priority. */
308  prio = DMA->CHPRIS;
309  pendingPrio = pending & prio;
310  for (i = 0; i < 2; i++)
311  {
312  channel = 0;
313  /* Process pending interrupts within high/default priority group */
314  /* honouring priority within group. */
315  while (pendingPrio)
316  {
317  if (pendingPrio & 1)
318  {
319  DMA_DESCRIPTOR_TypeDef *descr = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE);
320  uint32_t chmask = 1 << channel;
321 
322  /* Clear pending interrupt prior to invoking callback, in case it */
323  /* sets up another DMA cycle. */
324  DMA->IFC = chmask;
325 
326  /* Normally, no point in enabling interrupt without callback, but */
327  /* check if callback is defined anyway. Callback info is always */
328  /* located in primary descriptor. */
329  cb = (DMA_CB_TypeDef *)(descr[channel].USER);
330  if (cb)
331  {
332  /* Toggle next-descriptor indicator always prior to invoking */
333  /* callback (in case callback reconfigurs something) */
334  primaryCpy = cb->primary;
335  cb->primary ^= 1;
336  if (cb->cbFunc)
337  {
338  cb->cbFunc(channel, (bool)primaryCpy, cb->userPtr);
339  }
340  }
341  }
342 
343  pendingPrio >>= 1;
344  channel++;
345  }
346 
347  /* On second iteration, process default priority channels */
348  pendingPrio = pending & ~prio;
349  }
350 }
351 
352 #endif /* EXCLUDE_DEFAULT_DMA_IRQ_HANDLER */
353 
354 
355 /*******************************************************************************
356  ************************** GLOBAL FUNCTIONS *******************************
357  ******************************************************************************/
358 
359 /***************************************************************************/
391 void DMA_ActivateAuto(unsigned int channel,
392  bool primary,
393  void *dst,
394  void *src,
395  unsigned int nMinus1)
396 {
397  uint32_t chBit;
398 
399  EFM_ASSERT(channel < DMA_CHAN_COUNT);
400  EFM_ASSERT(nMinus1 <= (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT));
401 
402  DMA_Prepare(channel,
404  primary,
405  false,
406  dst,
407  src,
408  nMinus1);
409 
410  chBit = 1 << channel;
411  DMA->CHENS = chBit; /* Enable channel */
412  DMA->CHSWREQ = chBit; /* Activate with SW request */
413 }
414 
415 
416 /***************************************************************************/
454 void DMA_ActivateBasic(unsigned int channel,
455  bool primary,
456  bool useBurst,
457  void *dst,
458  void *src,
459  unsigned int nMinus1)
460 {
461  EFM_ASSERT(channel < DMA_CHAN_COUNT);
462  EFM_ASSERT(nMinus1 <= (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT));
463 
464  DMA_Prepare(channel,
466  primary,
467  useBurst,
468  dst,
469  src,
470  nMinus1);
471 
472  /* Enable channel, request signal is provided by peripheral device */
473  DMA->CHENS = 1 << channel;
474 }
475 
476 
477 /***************************************************************************/
526 void DMA_ActivatePingPong(unsigned int channel,
527  bool useBurst,
528  void *primDst,
529  void *primSrc,
530  unsigned int primNMinus1,
531  void *altDst,
532  void *altSrc,
533  unsigned int altNMinus1)
534 {
535  EFM_ASSERT(channel < DMA_CHAN_COUNT);
536  EFM_ASSERT(primNMinus1 <= (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT));
537  EFM_ASSERT(altNMinus1 <= (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT));
538 
539  /* Prepare alternate descriptor first */
540  DMA_Prepare(channel,
542  false,
543  useBurst,
544  altDst,
545  altSrc,
546  altNMinus1);
547 
548  /* Prepare primary descriptor last in order to start cycle using it */
549  DMA_Prepare(channel,
551  true,
552  useBurst,
553  primDst,
554  primSrc,
555  primNMinus1);
556 
557  /* Enable channel, request signal is provided by peripheral device */
558  DMA->CHENS = 1 << channel;
559 }
560 
561 
562 /***************************************************************************/
596 void DMA_ActivateScatterGather(unsigned int channel,
597  bool useBurst,
598  DMA_DESCRIPTOR_TypeDef *altDescr,
599  unsigned int count)
600 {
601  DMA_DESCRIPTOR_TypeDef *descr;
602  DMA_CB_TypeDef *cb;
603  uint32_t cycleCtrl;
604  uint32_t chBit;
605 
606  EFM_ASSERT(channel < DMA_CHAN_COUNT);
607  EFM_ASSERT(altDescr);
608  EFM_ASSERT(count && (count <= 256));
609 
610  /* We have to configure the primary descriptor properly in order to */
611  /* transfer one complete alternate descriptor from the alternate */
612  /* descriptor table into the actual alternate descriptor. */
613  descr = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE) + channel;
614 
615  /* Set source end address to point to alternate descriptor array */
616  descr->SRCEND = (uint32_t *)altDescr + (count * 4) - 1;
617 
618  /* The destination end address in the primary descriptor MUST point */
619  /* to the corresponding alternate descriptor in scatter-gather mode. */
620  descr->DSTEND = (uint32_t *)((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE) +
621  channel + 1) - 1;
622 
623  /* The user field of the descriptor is used for callback configuration, */
624  /* and already configured when channel is configured. Do not modify it. */
625 
626  /* Determine from alternate configuration whether this is a memory or */
627  /* peripheral scatter-gather, by looking at the first alternate descriptor. */
628  cycleCtrl = altDescr->CTRL & _DMA_CTRL_CYCLE_CTRL_MASK;
629  cycleCtrl &= ~(1 << _DMA_CTRL_CYCLE_CTRL_SHIFT);
630 
631  EFM_ASSERT((cycleCtrl == dmaCycleCtrlMemScatterGather)
632  || (cycleCtrl == dmaCycleCtrlPerScatterGather));
633 
634  /* Set last alternate descriptor to basic or auto-request cycle type in */
635  /* order to have dma_done signal asserted when complete. Otherwise interrupt */
636  /* will not be triggered when done. */
637  altDescr[count - 1].CTRL &= ~_DMA_CTRL_CYCLE_CTRL_MASK;
638  if (cycleCtrl == dmaCycleCtrlMemScatterGather)
639  {
640  altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlAuto
642  }
643  else
644  {
645  altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlBasic
647  }
648 
649  /* If callback defined, update info on whether callback is issued for */
650  /* primary or alternate descriptor. Not really useful for scatter-gather, */
651  /* but do for consistency. Always set to alternate, since that is the last */
652  /* descriptor actually used. */
653  cb = (DMA_CB_TypeDef *)(descr->USER);
654  if (cb)
655  {
656  cb->primary = false;
657  }
658 
659  /* Configure primary descriptor control word */
660  descr->CTRL =((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT)
661  | ((uint32_t)dmaDataSize4 << _DMA_CTRL_DST_SIZE_SHIFT)
662  | ((uint32_t)dmaDataInc4 << _DMA_CTRL_SRC_INC_SHIFT)
663  | ((uint32_t)dmaDataSize4 << _DMA_CTRL_SRC_SIZE_SHIFT)
664  /* Use same protection scheme as for alternate descriptors */
665  | (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK)
666  | ((uint32_t)dmaArbitrate4 << _DMA_CTRL_R_POWER_SHIFT)
667  | (((count * 4) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT)
668  | (((uint32_t)useBurst & 1) << _DMA_CTRL_NEXT_USEBURST_SHIFT)
669  | cycleCtrl;
670 
671  chBit = 1 << channel;
672 
673  /* Start with primary descriptor */
674  DMA->CHALTC = chBit;
675 
676  /* Enable channel */
677  DMA->CHENS = chBit;
678 
679  /* Send request if memory scatter-gather, otherwise request signal is */
680  /* provided by peripheral. */
681  if (cycleCtrl == dmaCycleCtrlMemScatterGather)
682  {
683  DMA->CHSWREQ = chBit;
684  }
685 }
686 
687 
688 /***************************************************************************/
706 void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg)
707 {
708  DMA_DESCRIPTOR_TypeDef *descr;
709 
710  EFM_ASSERT(channel < DMA_CHAN_COUNT);
711  EFM_ASSERT(cfg);
712 
713  /* Always keep callback configuration reference in primary descriptor */
714  descr = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE);
715  descr[channel].USER = (uint32_t)(cfg->cb);
716 
717  /* Set to specified priority for channel */
718  if (cfg->highPri)
719  {
720  DMA->CHPRIS = 1 << channel;
721  }
722  else
723  {
724  DMA->CHPRIC = 1 << channel;
725  }
726 
727  /* Set DMA signal source select */
728  DMA->CH[channel].CTRL = cfg->select;
729 
730  /* Enable/disable interrupt as specified */
731  if (cfg->enableInt)
732  {
733  DMA->IFC = (1 << channel);
734  BUS_RegBitWrite(&(DMA->IEN), channel, 1);
735  }
736  else
737  {
738  BUS_RegBitWrite(&(DMA->IEN), channel, 0);
739  }
740 }
741 
742 
743 /***************************************************************************/
781 void DMA_CfgDescr(unsigned int channel,
782  bool primary,
784 {
785  DMA_DESCRIPTOR_TypeDef *descr;
786 
787  EFM_ASSERT(channel < DMA_CHAN_COUNT);
788  EFM_ASSERT(cfg);
789 
790  /* Find descriptor to configure */
791  if (primary)
792  {
793  descr = (DMA_DESCRIPTOR_TypeDef *)DMA->CTRLBASE;
794  }
795  else
796  {
797  descr = (DMA_DESCRIPTOR_TypeDef *)DMA->ALTCTRLBASE;
798  }
799  descr += channel;
800 
801  /* Prepare the descriptor */
802  /* Source/destination end addresses set when started */
803  descr->CTRL = (cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
804  | (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
805  | (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
806  | (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
807  | ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
808  | (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
809  | (0 << _DMA_CTRL_N_MINUS_1_SHIFT) /* Set when activated */
810  | (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT) /* Set when activated */
811  | DMA_CTRL_CYCLE_CTRL_INVALID; /* Set when activated */
812 }
813 
814 
815 #if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
816 /***************************************************************************/
829 void DMA_CfgLoop(unsigned int channel, DMA_CfgLoop_TypeDef *cfg)
830 {
831  EFM_ASSERT(channel <= 1);
832  EFM_ASSERT(cfg->nMinus1 <= 1023);
833 
834  /* Configure LOOP setting */
835  switch( channel )
836  {
837  case 0:
838  DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT)
839  | (cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
840  break;
841  case 1:
842  DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT)
843  | (cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
844  break;
845  }
846 }
847 #endif
848 
849 
850 #if defined( _DMA_RECT0_MASK )
851 /***************************************************************************/
860 void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg)
861 {
862  (void)channel; /* Unused parameter */
863 
864  EFM_ASSERT(channel == 0);
865  EFM_ASSERT(cfg->dstStride <= 2047);
866  EFM_ASSERT(cfg->srcStride <= 2047);
867  EFM_ASSERT(cfg->height <= 1023);
868 
869  /* Configure rectangular/2D copy */
870  DMA->RECT0 = (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT)
872  | (cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
873 }
874 #endif
875 
876 
877 /***************************************************************************/
904  unsigned int indx,
906 {
907  uint32_t cycleCtrl;
908 
909  EFM_ASSERT(descr);
910  EFM_ASSERT(cfg);
911 
912  /* Point to selected entry in alternate descriptor table */
913  descr += indx;
914 
915  if (cfg->srcInc == dmaDataIncNone)
916  {
917  descr->SRCEND = cfg->src;
918  }
919  else
920  {
921  descr->SRCEND = (void *)((uint32_t)(cfg->src)
922  + ((uint32_t)(cfg->nMinus1) << cfg->srcInc));
923  }
924 
925  if (cfg->dstInc == dmaDataIncNone)
926  {
927  descr->DSTEND = cfg->dst;
928  }
929  else
930  {
931  descr->DSTEND = (void *)((uint32_t)(cfg->dst)
932  + ((uint32_t)(cfg->nMinus1) << cfg->dstInc));
933  }
934 
935  /* User definable part not used */
936  descr->USER = 0;
937 
938  if (cfg->peripheral)
939  {
940  cycleCtrl = (uint32_t)dmaCycleCtrlPerScatterGather + 1;
941  }
942  else
943  {
944  cycleCtrl = (uint32_t)dmaCycleCtrlMemScatterGather + 1;
945  }
946 
947  descr->CTRL =(cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
948  | (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
949  | (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
950  | (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
951  | ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
952  | (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
953  | ((uint32_t)(cfg->nMinus1) << _DMA_CTRL_N_MINUS_1_SHIFT)
954  /* Never set next useburst bit, since the descriptor used after the */
955  /* alternate descriptor is the primary descriptor which operates on */
956  /* memory. If the alternate descriptors need to have useBurst set, this */
957  /* done when setting up the primary descriptor, ie when activating. */
959  | (cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT);
960 }
961 
962 
963 /***************************************************************************/
979 void DMA_ChannelEnable(unsigned int channel, bool enable)
980 {
981  EFM_ASSERT(channel < DMA_CHAN_COUNT);
982 
983  if (enable)
984  {
985  DMA->CHENS = 1<<channel;
986  }
987  else
988  {
989  DMA->CHENC = 1<<channel;
990  }
991 }
992 
993 
994 /***************************************************************************/
1008 bool DMA_ChannelEnabled(unsigned int channel)
1009 {
1010  EFM_ASSERT(channel < DMA_CHAN_COUNT);
1011 
1012  return (bool)((DMA->CHENS >> channel) & 1);
1013 }
1014 
1015 
1016 /***************************************************************************/
1034 {
1035  EFM_ASSERT(init);
1036 
1037  /* Make sure control block is properly aligned */
1038 #if (DMA_CHAN_COUNT <= 4)
1039  EFM_ASSERT(!((uint32_t)(init->controlBlock) & (128 - 1)));
1040 #elif (DMA_CHAN_COUNT <= 8) || (DMA_CHAN_COUNT <= 12)
1041  EFM_ASSERT(!((uint32_t)(init->controlBlock) & (256 - 1)));
1042 #else
1043 #error "Unsupported DMA channel count (em_dma.c)."
1044 #endif
1045 
1046  /* Make sure DMA clock is enabled prior to accessing DMA module */
1048 
1049  /* Make sure DMA controller is set to a known reset state */
1050  DMA_Reset();
1051 
1052  /* Clear/enable DMA interrupts */
1053  NVIC_ClearPendingIRQ(DMA_IRQn);
1054  NVIC_EnableIRQ(DMA_IRQn);
1055 
1056  /* Enable bus error interrupt */
1057  DMA->IEN = DMA_IEN_ERR;
1058 
1059  /* Set pointer to control block, notice that this ptr must have been */
1060  /* properly aligned, according to requirements defined in the reference */
1061  /* manual. */
1062  DMA->CTRLBASE = (uint32_t)(init->controlBlock);
1063 
1064  /* Configure and enable the DMA controller */
1065  DMA->CONFIG = ((uint32_t)(init->hprot) << _DMA_CONFIG_CHPROT_SHIFT)
1066  | DMA_CONFIG_EN;
1067 }
1068 
1069 
1070 /***************************************************************************/
1111 void DMA_RefreshPingPong(unsigned int channel,
1112  bool primary,
1113  bool useBurst,
1114  void *dst,
1115  void *src,
1116  unsigned int nMinus1,
1117  bool stop)
1118 {
1119  DMA_CycleCtrl_TypeDef cycleCtrl;
1120  DMA_DESCRIPTOR_TypeDef *descr;
1121  uint32_t inc;
1122  uint32_t chBit;
1123  uint32_t tmp;
1124 
1125  EFM_ASSERT(channel < DMA_CHAN_COUNT);
1126  EFM_ASSERT(nMinus1 <= (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT));
1127 
1128  /* The ping-pong DMA cycle may be stopped by issuing a basic cycle type */
1129  if (stop)
1130  {
1131  cycleCtrl = dmaCycleCtrlBasic;
1132  }
1133  else
1134  {
1135  cycleCtrl = dmaCycleCtrlPingPong;
1136  }
1137 
1138  /* Find descriptor to configure */
1139  if (primary)
1140  {
1141  descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;
1142  }
1143  else
1144  {
1145  descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;
1146  }
1147 
1148  if (src)
1149  {
1151  if (inc == _DMA_CTRL_SRC_INC_NONE)
1152  {
1153  descr->SRCEND = src;
1154  }
1155  else
1156  {
1157  descr->SRCEND = (void *)((uint32_t)src + (nMinus1 << inc));
1158  }
1159  }
1160 
1161  if (dst)
1162  {
1164  if (inc == _DMA_CTRL_DST_INC_NONE)
1165  {
1166  descr->DSTEND = dst;
1167  }
1168  else
1169  {
1170  descr->DSTEND = (void *)((uint32_t)dst + (nMinus1 << inc));
1171  }
1172  }
1173 
1174  chBit = 1 << channel;
1175  if (useBurst)
1176  {
1177  DMA->CHUSEBURSTS = chBit;
1178  }
1179  else
1180  {
1181  DMA->CHUSEBURSTC = chBit;
1182  }
1183 
1184  /* Set cycle control */
1186  tmp |= nMinus1 << _DMA_CTRL_N_MINUS_1_SHIFT;
1187  tmp |= cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT;
1188  descr->CTRL = tmp;
1189 }
1190 
1191 
1192 /***************************************************************************/
1203 void DMA_Reset(void)
1204 {
1205  int i;
1206 
1207  /* Disable DMA interrupts */
1208  NVIC_DisableIRQ(DMA_IRQn);
1209 
1210  /* Put the DMA controller into a known state, first disabling it. */
1211  DMA->CONFIG = _DMA_CONFIG_RESETVALUE;
1212  DMA->CHUSEBURSTC = _DMA_CHUSEBURSTC_MASK;
1213  DMA->CHREQMASKC = _DMA_CHREQMASKC_MASK;
1214  DMA->CHENC = _DMA_CHENC_MASK;
1215  DMA->CHALTC = _DMA_CHALTC_MASK;
1216  DMA->CHPRIC = _DMA_CHPRIC_MASK;
1217  DMA->ERRORC = DMA_ERRORC_ERRORC;
1218  DMA->IEN = _DMA_IEN_RESETVALUE;
1219  DMA->IFC = _DMA_IFC_MASK;
1220 
1221  /* Clear channel control flags */
1222  for (i = 0; i < DMA_CHAN_COUNT; i++)
1223  {
1224  DMA->CH[i].CTRL = _DMA_CH_CTRL_RESETVALUE;
1225  }
1226 }
1227 
1228 
1231 #endif /* defined( DMA_PRESENT ) */
Clock management unit (CMU) API.
#define _DMA_CTRL_DST_INC_SHIFT
#define _DMA_CTRL_N_MINUS_1_MASK
DMA_DataSize_TypeDef size
Definition: em_dma.h:292
uint8_t hprot
Definition: em_dma.h:335
#define _DMA_CTRL_N_MINUS_1_SHIFT
#define _DMA_CTRL_SRC_INC_NONE
DMA_ArbiterConfig_TypeDef arbRate
Definition: em_dma.h:231
Emlib peripheral API "assert" implementation.
#define _DMA_CTRL_DST_SIZE_SHIFT
#define _DMA_RECT0_SRCSTRIDE_SHIFT
Definition: ezr32wg_dma.h:1455
DMA_DataInc_TypeDef dstInc
Definition: em_dma.h:219
Callback structure that can be used to define DMA complete actions.
Definition: em_dma.h:148
DMA_ArbiterConfig_TypeDef arbRate
Definition: em_dma.h:298
#define _DMA_RECT0_DSTSTRIDE_SHIFT
Definition: ezr32wg_dma.h:1459
RAM and peripheral bit-field set and clear API.
#define _DMA_CHPRIC_MASK
Definition: ezr32wg_dma.h:869
#define _DMA_CTRL_R_POWER_SHIFT
#define _DMA_CH_CTRL_RESETVALUE
Definition: ezr32wg_dma.h:1465
void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, void *src, unsigned int nMinus1, bool last)
Refresh a descriptor used in a DMA ping-pong cycle.
Definition: em_dma.c:1111
#define _DMA_LOOP0_EN_SHIFT
Definition: ezr32wg_dma.h:1430
void DMA_CfgDescrScatterGather(DMA_DESCRIPTOR_TypeDef *descr, unsigned int indx, DMA_CfgDescrSGAlt_TypeDef *cfg)
Configure an alternate DMA descriptor for use with scatter-gather DMA cycles.
Definition: em_dma.c:903
void DMA_IRQHandler(void)
Interrupt handler for DMA cycle completion handling.
Definition: em_dma.c:284
void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg)
Configure DMA channel 2D transfer properties.
Definition: em_dma.c:860
#define _DMA_CHUSEBURSTC_MASK
Definition: ezr32wg_dma.h:357
DMA_CB_TypeDef * cb
User definable callback handling configuration.
Definition: em_dma.h:208
DMA_DataInc_TypeDef srcInc
Definition: em_dma.h:289
#define DMA_CTRL_CYCLE_CTRL_INVALID
uint16_t srcStride
Definition: em_dma.h:269
#define _DMA_LOOP1_EN_SHIFT
Definition: ezr32wg_dma.h:1443
#define DMA_IF_ERR
Definition: ezr32wg_dma.h:1131
#define _DMA_CHREQMASKC_MASK
Definition: ezr32wg_dma.h:485
#define _DMA_CHALTC_MASK
Definition: ezr32wg_dma.h:741
bool DMA_ChannelEnabled(unsigned int channel)
Check if DMA channel is enabled.
Definition: em_dma.c:1008
#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT
#define _DMA_CONFIG_CHPROT_SHIFT
Definition: ezr32wg_dma.h:138
#define DMA_ERRORC_ERRORC
Definition: ezr32wg_dma.h:934
#define _DMA_CTRL_DST_INC_NONE
#define _DMA_IEN_RESETVALUE
Definition: ezr32wg_dma.h:1276
void DMA_Reset(void)
Reset the DMA controller.
Definition: em_dma.c:1203
#define _DMA_CTRL_CYCLE_CTRL_SHIFT
#define _DMA_CTRL_NEXT_USEBURST_SHIFT
#define _DMA_LOOP0_WIDTH_SHIFT
Definition: ezr32wg_dma.h:1425
#define _DMA_CONFIG_RESETVALUE
Definition: ezr32wg_dma.h:130
void DMA_CfgLoop(unsigned int channel, DMA_CfgLoop_TypeDef *cfg)
Configure DMA channel for Loop mode or 2D transfer.
Definition: em_dma.c:829
uint8_t primary
Definition: em_dma.h:165
uint16_t nMinus1
Definition: em_dma.h:255
void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, void *primSrc, unsigned int primNMinus1, void *altDst, void *altSrc, unsigned int altNMinus1)
Activate DMA ping-pong cycle (used for memory-peripheral transfers).
Definition: em_dma.c:526
#define _DMA_CTRL_CYCLE_CTRL_MASK
#define _DMA_CTRL_SRC_INC_SHIFT
#define _DMA_LOOP1_WIDTH_SHIFT
Definition: ezr32wg_dma.h:1438
void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, void *src, unsigned int nMinus1)
Activate DMA basic cycle (used for memory-peripheral transfers).
Definition: em_dma.c:454
void DMA_Init(DMA_Init_TypeDef *init)
Initializes DMA controller.
Definition: em_dma.c:1033
void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg)
Configure a DMA channel.
Definition: em_dma.c:706
#define _DMA_CTRL_SRC_INC_MASK
#define DMA_CHAN_COUNT
DMA_DataSize_TypeDef size
Definition: em_dma.h:225
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
Definition: em_cmu.c:1369
DMA_DataInc_TypeDef srcInc
Definition: em_dma.h:222
uint16_t dstStride
Definition: em_dma.h:267
#define DMA_IEN_ERR
Definition: ezr32wg_dma.h:1338
DMA_DataInc_TypeDef dstInc
Definition: em_dma.h:286
void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, void *src, unsigned int nMinus1)
Activate DMA auto-request cycle (used for memory-memory transfers).
Definition: em_dma.c:391
DMA_DESCRIPTOR_TypeDef * controlBlock
Definition: em_dma.h:352
#define DMA
void * userPtr
Definition: em_dma.h:158
DMA_CycleCtrl_TypeDef
Definition: em_dma.h:83
DMA_FuncPtr_TypeDef cbFunc
Definition: em_dma.h:155
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146
void DMA_ActivateScatterGather(unsigned int channel, bool useBurst, DMA_DESCRIPTOR_TypeDef *altDescr, unsigned int count)
Activate DMA scatter-gather cycle (used for either memory-peripheral or memory-memory transfers)...
Definition: em_dma.c:596
#define _DMA_CHENC_MASK
Definition: ezr32wg_dma.h:613
#define DMA_CONFIG_EN
Definition: ezr32wg_dma.h:132
Direct memory access (DMA) API.
#define _DMA_CTRL_SRC_PROT_CTRL_MASK
uint16_t height
Definition: em_dma.h:271
#define _DMA_RECT0_HEIGHT_SHIFT
Definition: ezr32wg_dma.h:1451
#define _DMA_IFC_MASK
Definition: ezr32wg_dma.h:1208
void DMA_ChannelEnable(unsigned int channel, bool enable)
Enable or disable a DMA channel.
Definition: em_dma.c:979
#define _DMA_CTRL_SRC_SIZE_SHIFT
#define _DMA_CTRL_DST_INC_MASK
void DMA_CfgDescr(unsigned int channel, bool primary, DMA_CfgDescr_TypeDef *cfg)
Configure DMA descriptor for auto-request, basic or ping-pong DMA cycles.
Definition: em_dma.c:781